From 87bfa955bd360eaaf0246acc855e28e38b3d9f76 Mon Sep 17 00:00:00 2001 From: Jiyu Yang Date: Wed, 13 Mar 2019 10:30:06 +0800 Subject: [PATCH] dts: use mesong12a-bifrost instead [1/1] PD#SWPL-5865 Problem: SM1 bring up Solution: commit dts for SM1 bringup Verify: PxP Change-Id: Ifdbc751e2fa9ecb3d747c114ac820ab60021294d Signed-off-by: Jiyu Yang --- MAINTAINERS | 2 - arch/arm/boot/dts/amlogic/mesonsm1-bifrost.dtsi | 128 ---------------------- arch/arm/boot/dts/amlogic/mesonsm1.dtsi | 2 +- arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi | 128 ---------------------- arch/arm64/boot/dts/amlogic/mesonsm1.dtsi | 2 +- 5 files changed, 2 insertions(+), 260 deletions(-) delete mode 100644 arch/arm/boot/dts/amlogic/mesonsm1-bifrost.dtsi delete mode 100644 arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 79f77ba..982e1bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14811,9 +14811,7 @@ F: sound/soc/codecs/amlogic/tas5782m.h AMLOGIC SM1 DTS M: Zhiqiang Liang -F: arch/arm64/boot/dts/amlogic/mesongsm1-bifrost.dtsi F: arch/arm64/boot/dts/amlogic/mesongsm1.dtsi F: arch/arm64/boot/dts/amlogic/sm1_pxp.dts -F: arch/arm/boot/dts/amlogic/mesonsm1-bifrost.dtsi F: arch/arm/boot/dts/amlogic/mesonsm1.dtsi F: arch/arm/boot/dts/amlogic/sm1_pxp.dts diff --git a/arch/arm/boot/dts/amlogic/mesonsm1-bifrost.dtsi b/arch/arm/boot/dts/amlogic/mesonsm1-bifrost.dtsi deleted file mode 100644 index 5875d72..0000000 --- a/arch/arm/boot/dts/amlogic/mesonsm1-bifrost.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -/* - * arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi - * - * Copyright (C) 2017 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - - gpu:bifrost { - compatible = "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; - #cooling-cells = <2>; /* min followed by max */ - reg = <0xFFE40000 0x04000>, /*mali APB bus base address*/ - <0xFFD01000 0x01000>, /*reset register*/ - <0xFF800000 0x01000>, /*aobus for gpu pmu domain*/ - <0xFF63c000 0x01000>, /*hiubus for gpu clk cntl*/ - <0xFFD01000 0x01000>; /*reset register*/ - interrupt-parent = <&gic>; - interrupts = <0 160 4>, <0 161 4>, <0 162 4>; - interrupt-names = "GPU", "MMU", "JOB"; - /* ACE-Lite = 0; ACE = 1; No-coherency = 31; */ - /* system-coherency = <31>; */ - - num_of_pp = <2>; - sc_mpp = <1>; /* number of shader cores used most of time. */ - clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; - clock-names = "gpu_mux","gp0_pll"; - - - tbl = <&dvfs285_cfg - &dvfs400_cfg - &dvfs500_cfg - &dvfs666_cfg - &dvfs850_cfg - &dvfs850_cfg>; - - dvfs125_cfg:clk125_cfg { - clk_freq = <125000000>; - clk_parent = "fclk_div4"; - clkp_freq = <500000000>; - clk_reg = <0xA03>; - voltage = <1150>; - keep_count = <5>; - threshold = <30 120>; - }; - - dvfs250_cfg:dvfs250_cfg { - clk_freq = <250000000>; - clk_parent = "fclk_div4"; - clkp_freq = <500000000>; - clk_reg = <0xA01>; - voltage = <1150>; - keep_count = <5>; - threshold = <80 170>; - }; - - dvfs285_cfg:dvfs285_cfg { - clk_freq = <285714285>; - clk_parent = "fclk_div7"; - clkp_freq = <285714285>; - clk_reg = <0xE00>; - voltage = <1150>; - keep_count = <5>; - threshold = <100 190>; - }; - - dvfs400_cfg:dvfs400_cfg { - clk_freq = <400000000>; - clk_parent = "fclk_div5"; - clkp_freq = <400000000>; - clk_reg = <0xC00>; - voltage = <1150>; - keep_count = <5>; - threshold = <152 207>; - }; - - dvfs500_cfg:dvfs500_cfg { - clk_freq = <500000000>; - clk_parent = "fclk_div4"; - clkp_freq = <500000000>; - clk_reg = <0xA00>; - voltage = <1150>; - keep_count = <5>; - threshold = <180 220>; - }; - - dvfs666_cfg:dvfs666_cfg { - clk_freq = <666666666>; - clk_parent = "fclk_div3"; - clkp_freq = <666666666>; - clk_reg = <0x800>; - voltage = <1150>; - keep_count = <5>; - threshold = <210 236>; - }; - - dvfs800_cfg:dvfs800_cfg { - clk_freq = <800000000>; - clk_parent = "fclk_div2p5"; - clkp_freq = <800000000>; - clk_reg = <0x600>; - voltage = <1150>; - keep_count = <5>; - threshold = <230 255>; - }; - - dvfs850_cfg:dvfs850_cfg { - clk_freq = <846000000>; - clk_parent = "gp0_pll"; - clkp_freq = <846000000>; - clk_reg = <0x200>; - voltage = <1150>; - keep_count = <5>; - threshold = <230 255>; - }; - }; - -};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi index 745d380..4917771 100644 --- a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi @@ -26,7 +26,7 @@ #include #include #include -#include "mesonsm1-bifrost.dtsi" +#include "mesong12a-bifrost.dtsi" / { cpus:cpus { diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi deleted file mode 100644 index 99fe151..0000000 --- a/arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -/* - * arch/arm64/boot/dts/amlogic/mesonsm1-bifrost.dtsi - * - * Copyright (C) 2017 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - - gpu:bifrost { - compatible = "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; - #cooling-cells = <2>; /* min followed by max */ - reg = <0 0xFFE40000 0 0x04000>, /*mali APB bus base address*/ - <0 0xFFD01000 0 0x01000>, /*reset register*/ - <0 0xFF800000 0 0x01000>, /*aobus for gpu pmu domain*/ - <0 0xFF63c000 0 0x01000>, /*hiubus for gpu clk cntl*/ - <0 0xFFD01000 0 0x01000>; /*reset register*/ - interrupt-parent = <&gic>; - interrupts = <0 160 4>, <0 161 4>, <0 162 4>; - interrupt-names = "GPU", "MMU", "JOB"; - /* ACE-Lite = 0; ACE = 1; No-coherency = 31; */ - /* system-coherency = <31>; */ - - num_of_pp = <2>; - sc_mpp = <1>; /* number of shader cores used most of time. */ - clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; - clock-names = "gpu_mux","gp0_pll"; - - - tbl = <&dvfs285_cfg - &dvfs400_cfg - &dvfs500_cfg - &dvfs666_cfg - &dvfs850_cfg - &dvfs850_cfg>; - - dvfs125_cfg:clk125_cfg { - clk_freq = <125000000>; - clk_parent = "fclk_div4"; - clkp_freq = <500000000>; - clk_reg = <0xA03>; - voltage = <1150>; - keep_count = <5>; - threshold = <30 120>; - }; - - dvfs250_cfg:dvfs250_cfg { - clk_freq = <250000000>; - clk_parent = "fclk_div4"; - clkp_freq = <500000000>; - clk_reg = <0xA01>; - voltage = <1150>; - keep_count = <5>; - threshold = <80 170>; - }; - - dvfs285_cfg:dvfs285_cfg { - clk_freq = <285714285>; - clk_parent = "fclk_div7"; - clkp_freq = <285714285>; - clk_reg = <0xE00>; - voltage = <1150>; - keep_count = <5>; - threshold = <100 190>; - }; - - dvfs400_cfg:dvfs400_cfg { - clk_freq = <400000000>; - clk_parent = "fclk_div5"; - clkp_freq = <400000000>; - clk_reg = <0xC00>; - voltage = <1150>; - keep_count = <5>; - threshold = <152 207>; - }; - - dvfs500_cfg:dvfs500_cfg { - clk_freq = <500000000>; - clk_parent = "fclk_div4"; - clkp_freq = <500000000>; - clk_reg = <0xA00>; - voltage = <1150>; - keep_count = <5>; - threshold = <180 220>; - }; - - dvfs666_cfg:dvfs666_cfg { - clk_freq = <666666666>; - clk_parent = "fclk_div3"; - clkp_freq = <666666666>; - clk_reg = <0x800>; - voltage = <1150>; - keep_count = <5>; - threshold = <210 236>; - }; - - dvfs800_cfg:dvfs800_cfg { - clk_freq = <800000000>; - clk_parent = "fclk_div2p5"; - clkp_freq = <800000000>; - clk_reg = <0x600>; - voltage = <1150>; - keep_count = <5>; - threshold = <230 255>; - }; - - dvfs850_cfg:dvfs850_cfg { - clk_freq = <846000000>; - clk_parent = "gp0_pll"; - clkp_freq = <846000000>; - clk_reg = <0x200>; - voltage = <1150>; - keep_count = <5>; - threshold = <230 255>; - }; - }; - -};/* end of / */ diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi index 91d55eb..2e0b1fd 100644 --- a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi @@ -26,7 +26,7 @@ #include #include #include -#include "mesonsm1-bifrost.dtsi" +#include "mesong12a-bifrost.dtsi" / { cpus:cpus { -- 2.7.4