From 87873d04c3401ecd91bbdd38b2b84b1f6bc0b1e4 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Tue, 9 Oct 2018 20:35:15 +0000 Subject: [PATCH] [PowerPC] Implement hasBitPreservingFPLogic for types that can be supported This is the PPC-specific non-controversial part of https://reviews.llvm.org/D44548 that simply enables this combine for PPC since PPC has these instructions. This commit will allow the target-independent portion to be truly target independent. llvm-svn: 344077 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 9 ++ llvm/lib/Target/PowerPC/PPCISelLowering.h | 1 + llvm/test/CodeGen/PowerPC/float-logic-ops.ll | 126 +++++++++++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/float-logic-ops.ll diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 1e51393..f4fd8e1 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14320,6 +14320,15 @@ bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const { return getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), Callee); } +bool PPCTargetLowering::hasBitPreservingFPLogic(EVT VT) const { + if (!Subtarget.hasVSX()) + return false; + if (Subtarget.hasP9Vector() && VT == MVT::f128) + return true; + return VT == MVT::f32 || VT == MVT::f64 || + VT == MVT::v4f32 || VT == MVT::v2f64; +} + bool PPCTargetLowering:: isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const { const Value *Mask = AndI.getOperand(1); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 0872ac2..9709d6b 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1127,6 +1127,7 @@ namespace llvm { // tail call. This will cause the optimizers to attempt to move, or // duplicate return instructions to help enable tail call optimizations. bool mayBeEmittedAsTailCall(const CallInst *CI) const override; + bool hasBitPreservingFPLogic(EVT VT) const override; bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; }; // end class PPCTargetLowering diff --git a/llvm/test/CodeGen/PowerPC/float-logic-ops.ll b/llvm/test/CodeGen/PowerPC/float-logic-ops.ll new file mode 100644 index 0000000..70b6cd4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/float-logic-ops.ll @@ -0,0 +1,126 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unkknown-unknown \ +; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s + +define float @absf(float %a) { +; CHECK-LABEL: absf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fabs f1, f1 +; CHECK-NEXT: blr +entry: + %conv = bitcast float %a to i32 + %and = and i32 %conv, 2147483647 + %conv1 = bitcast i32 %and to float + ret float %conv1 +} + +define double @absd(double %a) { +; CHECK-LABEL: absd: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsabsdp f1, f1 +; CHECK-NEXT: blr +entry: + %conv = bitcast double %a to i64 + %and = and i64 %conv, 9223372036854775807 + %conv1 = bitcast i64 %and to double + ret double %conv1 +} + +define <4 x float> @absv4f32(<4 x float> %a) { +; CHECK-LABEL: absv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvabssp vs34, vs34 +; CHECK-NEXT: blr +entry: + %conv = bitcast <4 x float> %a to <4 x i32> + %and = and <4 x i32> %conv, + %conv1 = bitcast <4 x i32> %and to <4 x float> + ret <4 x float> %conv1 +} + +define <4 x float> @absv4f32_wundef(<4 x float> %a) { +; CHECK-LABEL: absv4f32_wundef: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvabssp vs34, vs34 +; CHECK-NEXT: blr +entry: + %conv = bitcast <4 x float> %a to <4 x i32> + %and = and <4 x i32> %conv, + %conv1 = bitcast <4 x i32> %and to <4 x float> + ret <4 x float> %conv1 +} + +define <4 x float> @absv4f32_invalid(<4 x float> %a) { +; CHECK-LABEL: absv4f32_invalid: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-NEXT: lvx v3, 0, r3 +; CHECK-NEXT: xxland vs34, vs34, vs35 +; CHECK-NEXT: blr +entry: + %conv = bitcast <4 x float> %a to <4 x i32> + %and = and <4 x i32> %conv, + %conv1 = bitcast <4 x i32> %and to <4 x float> + ret <4 x float> %conv1 +} + +define <2 x double> @absv2f64(<2 x double> %a) { +; CHECK-LABEL: absv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvabsdp vs34, vs34 +; CHECK-NEXT: blr +entry: + %conv = bitcast <2 x double> %a to <2 x i64> + %and = and <2 x i64> %conv, + %conv1 = bitcast <2 x i64> %and to <2 x double> + ret <2 x double> %conv1 +} + +define float @negf(float %a) { +; CHECK-LABEL: negf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fneg f1, f1 +; CHECK-NEXT: blr +entry: + %conv = bitcast float %a to i32 + %and = xor i32 %conv, -2147483648 + %conv1 = bitcast i32 %and to float + ret float %conv1 +} + +define double @negd(double %a) { +; CHECK-LABEL: negd: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xsnegdp f1, f1 +; CHECK-NEXT: blr +entry: + %conv = bitcast double %a to i64 + %and = xor i64 %conv, -9223372036854775808 + %conv1 = bitcast i64 %and to double + ret double %conv1 +} + +define <4 x float> @negv4f32(<4 x float> %a) { +; CHECK-LABEL: negv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvnegsp vs34, vs34 +; CHECK-NEXT: blr +entry: + %conv = bitcast <4 x float> %a to <4 x i32> + %and = xor <4 x i32> %conv, + %conv1 = bitcast <4 x i32> %and to <4 x float> + ret <4 x float> %conv1 +} + +define <2 x double> @negv2d64(<2 x double> %a) { +; CHECK-LABEL: negv2d64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvnegdp vs34, vs34 +; CHECK-NEXT: blr +entry: + %conv = bitcast <2 x double> %a to <2 x i64> + %and = xor <2 x i64> %conv, + %conv1 = bitcast <2 x i64> %and to <2 x double> + ret <2 x double> %conv1 +} -- 2.7.4