From 8737fc7529cf863549d8e5bd631a47008302086f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 15 Dec 2014 23:26:11 +0900 Subject: [PATCH] mpc8xx: remove RRvision board support This board is still a non-generic board. Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177, CONFIG_VIDEO_ENCODER_AD7179 are not defined any more. Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk --- arch/powerpc/cpu/mpc8xx/Kconfig | 4 - arch/powerpc/cpu/mpc8xx/video.c | 148 ------------ board/RRvision/Kconfig | 9 - board/RRvision/MAINTAINERS | 7 - board/RRvision/Makefile | 8 - board/RRvision/RRvision.c | 222 ------------------ board/RRvision/flash.c | 506 ---------------------------------------- board/RRvision/u-boot.lds | 87 ------- board/RRvision/video_ad7179.h | 52 ----- configs/RRvision_LCD_defconfig | 4 - configs/RRvision_defconfig | 3 - doc/README.scrapyard | 1 + drivers/video/mpc8xx_lcd.c | 17 -- include/commproc.h | 5 +- include/configs/RRvision.h | 450 ----------------------------------- include/video_ad7176.h | 89 ------- include/video_ad7177.h | 133 ----------- include/video_ad7179.h | 20 -- 18 files changed, 3 insertions(+), 1762 deletions(-) delete mode 100644 board/RRvision/Kconfig delete mode 100644 board/RRvision/MAINTAINERS delete mode 100644 board/RRvision/Makefile delete mode 100644 board/RRvision/RRvision.c delete mode 100644 board/RRvision/flash.c delete mode 100644 board/RRvision/u-boot.lds delete mode 100644 board/RRvision/video_ad7179.h delete mode 100644 configs/RRvision_LCD_defconfig delete mode 100644 configs/RRvision_defconfig delete mode 100644 include/configs/RRvision.h delete mode 100644 include/video_ad7176.h delete mode 100644 include/video_ad7177.h delete mode 100644 include/video_ad7179.h diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 8bda42e..37ee5f6 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -31,9 +31,6 @@ config TARGET_NETVIA config TARGET_R360MPI bool "Support R360MPI" -config TARGET_RRVISION - bool "Support RRvision" - config TARGET_TQM823L bool "Support TQM823L" @@ -72,7 +69,6 @@ config TARGET_TQM885D endchoice -source "board/RRvision/Kconfig" source "board/cogent/Kconfig" source "board/esteem192e/Kconfig" source "board/ip860/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 9590bfd..659e688 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -53,34 +53,6 @@ DECLARE_GLOBAL_DATA_PTR; #define VIDEO_INFO_Y 16 /************************************************************************/ -/* ** VIDEO ENCODER CONSTANTS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_ENCODER_AD7176 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7176_ADDR -#endif - -#ifdef CONFIG_VIDEO_ENCODER_AD7177 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR -#endif - -#ifdef CONFIG_VIDEO_ENCODER_AD7179 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR -#endif - -/************************************************************************/ /* ** VIDEO MODE CONSTANTS */ /************************************************************************/ @@ -467,7 +439,6 @@ static inline void video_putstring (int xx, int yy, unsigned char *s) /* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ /************************************************************************/ -#if !defined(CONFIG_RRVISION) static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) { int i; @@ -480,7 +451,6 @@ static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) dest[0].lcyc++; /* Add a cycle to the first entry */ dest[entries - 1].lst = 1; /* Set end of ram entries */ } -#endif static void inline video_mode_addentry (VRAM * vr, int Hx, int Vx, int Fx, int Bx, @@ -641,72 +611,6 @@ static int video_mode_generate (void) #ifdef VIDEO_MODE_PAL -#if defined(CONFIG_RRVISION) - -#define HPW 160 /* horizontal pulse width (was 139) */ -#define VPW 2 /* vertical pulse width */ -#define HBP 104 /* horizontal back porch (was 112) */ -#define VBP 19 /* vertical back porch (was 19) */ -#define VID_R 240 /* number of rows */ - - debug ("[VIDEO CTRL] Starting to add controller entries..."); -/* - * Even field - */ - ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); - - ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); - - ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); -/* - * Active area - */ - ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); - ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); - - ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); -/* - * Odd field - */ - ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); - - ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); - - ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); -/* - * Active area - */ - ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); - ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); - - ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); - - debug ("done\n"); - -#else /* !CONFIG_RRVISION */ - /* * Hx Vx Fx Bx VDS INT LCYC LP LST * @@ -758,7 +662,6 @@ static int video_mode_generate (void) * one more cycle loop and a last identifier) */ video_mode_dupefield (vr, &vr[entry], entry); -#endif /* CONFIG_RRVISION */ #endif /* VIDEO_MODE_PAL */ @@ -787,42 +690,6 @@ static int video_mode_generate (void) static void video_encoder_init (void) { -#ifdef VIDEO_I2C - int rc; - - /* Initialize the I2C */ - debug ("[VIDEO ENCODER] Initializing I2C bus...\n"); -#ifdef CONFIG_SYS_I2C - i2c_init_all(); -#else - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - /* Send configuration */ -#ifdef DEBUG - { - int i; - - puts ("[VIDEO ENCODER] Configuring the encoder...\n"); - - printf ("Sending %zu bytes (@ %08lX) to I2C 0x%lX:\n ", - sizeof(video_encoder_data), - (ulong)video_encoder_data, - (ulong)VIDEO_I2C_ADDR); - for (i=0; iim_ioport.iop_pdpar = 0x1fff; immap->im_ioport.iop_pddir = 0x0000; -#ifdef CONFIG_RRVISION - debug ("PC5->Output(1): enable PAL clock"); - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcdir |= 0x0400 ; - immap->im_ioport.iop_pcdat |= 0x0400 ; - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immap->im_ioport.iop_pdpar, - immap->im_ioport.iop_pddir, - immap->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immap->im_ioport.iop_pcpar, - immap->im_ioport.iop_pcdir, - immap->im_ioport.iop_pcdat); -#endif /* CONFIG_RRVISION */ - /* Blanking the screen. */ debug ("[VIDEO CTRL] Blanking the screen...\n"); video_fill (VIDEO_BG_COL); diff --git a/board/RRvision/Kconfig b/board/RRvision/Kconfig deleted file mode 100644 index 7c8a6f6..0000000 --- a/board/RRvision/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_RRVISION - -config SYS_BOARD - default "RRvision" - -config SYS_CONFIG_NAME - default "RRvision" - -endif diff --git a/board/RRvision/MAINTAINERS b/board/RRvision/MAINTAINERS deleted file mode 100644 index 59b5c5f..0000000 --- a/board/RRvision/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -RRVISION BOARD -M: Wolfgang Denk -S: Maintained -F: board/RRvision/ -F: include/configs/RRvision.h -F: configs/RRvision_defconfig -F: configs/RRvision_LCD_defconfig diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile deleted file mode 100644 index 908e8f8..0000000 --- a/board/RRvision/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RRvision.o flash.o diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c deleted file mode 100644 index d94e238..0000000 --- a/board/RRvision/RRvision.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank). - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: RRvision "); - - for (i=0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long reg; - long int size8, size9; - long int size = 0; - - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 the SDRAM bank 2 at physical address 0. - */ - memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c deleted file mode 100644 index 146a923..0000000 --- a/board/RRvision/flash.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define DEBUG - -#include -#include - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - puts ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - puts ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { - case AMD_ID_LV400B: - case AMD_ID_LV800B: - case AMD_ID_LV160B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV400T: - case AMD_ID_LV800T: - case AMD_ID_LV160T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_LV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - case AMD_ID_LV320T: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The last 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < (info->sector_count - 8)) - ? 2 * (64 << 10) - : 2 * ( 8 << 10); - } - break; - default: - return (0); - break; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds deleted file mode 100644 index 9470a24..0000000 --- a/board/RRvision/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - . = env_offset; - common/env_embedded.o (.ppcenv) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RRvision/video_ad7179.h b/board/RRvision/video_ad7179.h deleted file mode 100644 index 1fc1ef4..0000000 --- a/board/RRvision/video_ad7179.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7179" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#else -#error "NTSC mode is not supported" -#endif - -static unsigned char video_encoder_data[] = { - 0x05, /* Mode Register 0 */ - 0x11, /* Mode Register 1 */ - 0x20, /* Mode Register 2 */ - 0x0C, /* Mode Register 3 */ - 0x01, /* Mode Register 4 */ - 0x00, /* Reserved */ - 0x00, /* Reserved */ - 0x04, /* Timing Register 0 */ - 0x00, /* Timing Register 1 */ - 0xCB, /* Subcarrier Frequency Register 0 */ - 0x0A, /* Subcarrier Frequency Register 1 */ - 0x09, /* Subcarrier Frequency Register 2 */ - 0x2A, /* Subcarrier Frequency Register 3 */ - 0x00, /* Subcarrier Phase */ - 0x00, /* Closed Captioning Ext Reg 0 */ - 0x00, /* Closed Captioning Ext Reg 1 */ - 0x00, /* Closed Captioning Reg 0 */ - 0x00, /* Closed Captioning Reg 1 */ - 0x00, /* Pedestal Control Reg 0 */ - 0x00, /* Pedestal Control Reg 1 */ - 0x00, /* Pedestal Control Reg 2 */ - 0x00, /* Pedestal Control Reg 3 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00 /* Teletext Req. Control Reg */ -} ; diff --git a/configs/RRvision_LCD_defconfig b/configs/RRvision_LCD_defconfig deleted file mode 100644 index 4d61187..0000000 --- a/configs/RRvision_LCD_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01" -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_RRVISION=y diff --git a/configs/RRvision_defconfig b/configs/RRvision_defconfig deleted file mode 100644 index bdb4d7a..0000000 --- a/configs/RRvision_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_RRVISION=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 623a30e..00a5447 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +RRvision powerpc mpc8xx - - Wolfgang Denk SPD823TS powerpc mpc8xx - - Wolfgang Denk KUP4K powerpc mpc8xx - - Klaus Heydeck KUP4X powerpc mpc8xx - - Klaus Heydeck diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c index 2bc3ceb..a5c1e19 100644 --- a/drivers/video/mpc8xx_lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -448,23 +448,6 @@ void lcd_enable (void) r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); } #endif /* CONFIG_R360MPI */ -#ifdef CONFIG_RRVISION - debug ("PC4->Output(1): enable LVDS\n"); - debug ("PC5->Output(0): disable PAL clock\n"); - immr->im_ioport.iop_pddir |= 0x1000; - immr->im_ioport.iop_pcpar &= ~(0x0C00); - immr->im_ioport.iop_pcdir |= 0x0C00 ; - immr->im_ioport.iop_pcdat |= 0x0800 ; - immr->im_ioport.iop_pcdat &= ~(0x0400); - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immr->im_ioport.iop_pdpar, - immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, - immr->im_ioport.iop_pcdat); -#endif } /************************************************************************/ diff --git a/include/commproc.h b/include/commproc.h index 4c39934..7d62861 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -631,10 +631,9 @@ typedef struct scc_enet { #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ defined(CONFIG_R360MPI) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ + defined(CONFIG_TQM823L) || \ defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ - defined(CONFIG_RRVISION) + defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h deleted file mode 100644 index 97f7798..0000000 --- a/include/configs/RRvision.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_RRVISION 1 /* ...on a RRvision board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_GCLK_FREQ 64000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "setenv stdout serial" - -#undef CONFIG_BOOTARGS -#define CONFIG_ETHADDR 00:50:C2:00:E0:70 -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_IPADDR 10.0.0.5 -#define CONFIG_SERVERIP 10.0.0.2 -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_ROOTPATH "/opt/eldk/ppc_8xx" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \ - ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "load=tftp 100000 /tftpboot/u-boot.bin\0" \ - "update=protect off 1:0-8;era 1:0-8;" \ - "cp.b 100000 40000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "kernel_img=/tftpboot/uImage\0" \ - "kernel_load=tftp 200000 ${kernel_img}\0" \ - "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ - "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" - - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* disturbs display */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -#ifdef CONFIG_LCD -#define CONFIG_MPC8XX_LCD -#else -#define CONFIG_VIDEO 1 /* To enable the video initialization */ - -/* Video related */ -#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ -#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */ -#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */ -#endif - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE - -#undef CONFIG_CMD_PCMCIA -#undef CONFIG_CMD_IDE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -/* timeout values are in ticks = ms */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (120*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ - -/* for 64 MHz, we use a 16 MHz clock * 4 */ -#define CONFIG_SYS_PLPRCR ( (4-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#define CONFIG_SYS_MAMR_PTA 129 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -#endif /* __CONFIG_H */ diff --git a/include/video_ad7176.h b/include/video_ad7176.h deleted file mode 100644 index 6a0230e..0000000 --- a/include/video_ad7176.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VIDEO_AD7176_H_ -#define _VIDEO_AD7176_H_ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7176" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#endif - -#ifdef VIDEO_MODE_NTSC -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 525 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 400 -#endif - -static unsigned char video_encoder_data[] = { -#ifdef VIDEO_MODE_NTSC - 0x04, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0x82, -#else - 0x02, /* Mode Register 1 */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0x16, /* Subcarrier Freq 0 */ - 0x7c, /* Subcarrier Freq 1 */ - 0xf0, /* Subcarrier Freq 2 */ - 0x21, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x00 /* Mode Register 3 */ - -#endif /* VIDEO_MODE_NTSC */ - -#ifdef VIDEO_MODE_PAL - 0x05, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0x82, -#else - 0x02, /* Mode Register 1 (2) */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x0a, /* Timing Register 0 (a) */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 (8) */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x00 /* Mode Register 3 */ -#endif /* VIDEO_MODE_PAL */ -} ; - -#endif /* _VIDEO_AD7176_H_ */ diff --git a/include/video_ad7177.h b/include/video_ad7177.h deleted file mode 100644 index 38436d6..0000000 --- a/include/video_ad7177.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VIDEO_AD7177_H_ -#define _VIDEO_AD7177_H_ - -/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7177" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#endif - -#ifdef VIDEO_MODE_NTSC -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 525 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 400 -#endif - -static unsigned char - video_encoder_data[] = { -#ifdef VIDEO_MODE_NTSC - 0x04, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0xc2, -#else - 0x42, /* Mode Register 1 */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0x16, /* Subcarrier Freq 0 */ - 0x7c, /* Subcarrier Freq 1 */ - 0xf0, /* Subcarrier Freq 2 */ - 0x21, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08, /* Mode Register 3 */ - -#endif /* VIDEO_MODE_NTSC */ - -#ifdef VIDEO_MODE_PAL -#ifdef VIDEO_MODE_RGB_OUT - - 0x69, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0xc0, /* Mode Register 1 (c0) */ -#else - 0x40, /* Mode Register 1 (c0) */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x28, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08, /* Mode Register 3 */ - -#else /* ! VIDEO_MODE_RGB_OUT */ - - 0x09, /* Mode Register 0 (was 01) */ -#ifdef VIDEO_DEBUG_COLORBARS - 0xd8, /* */ -#else - 0x59, /* Mode Register 1 (was 58) */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 (was a) */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ -#ifdef VIDEO_DEBUG_LOWPOWER -#ifdef VIDEO_DEBUG_DISABLE_COLORS - 0x98, /* Mode Register 2 */ -#else - 0x88, /* Mode Register 2 */ -#endif /* VIDEO_DEBUG_DISABLE_COLORS */ -#else /* ! VIDEO_DEBUG_LOWPOWER */ -#ifdef VIDEO_DEBUG_DISABLE_COLORS - 0x18, /* Mode Register 2 */ -#else - 0x08, /* Mode Register 2 */ -#endif /* VIDEO_DEBUG_DISABLE_COLORS */ -#endif /* VIDEO_DEBUG_LOWPOWER */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08 /* Mode Register 3 */ -#endif /* VIDEO_MODE_RGB_OUT */ -#endif /* VIDEO_MODE_PAL */ - } ; - -#endif /* _VIDEO_AD7177_H_ */ diff --git a/include/video_ad7179.h b/include/video_ad7179.h deleted file mode 100644 index 67c1ec0..0000000 --- a/include/video_ad7179.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2003 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VIDEO_AD7179_H_ -#define _VIDEO_AD7179_H_ - -/* - * The video encoder data are board specific now! - */ - -#if defined(CONFIG_RRVISION) -#include "../board/RRvision/video_ad7179.h" -#else -#error "Please provide a board-specific video_ad7179.h" -#endif - -#endif /* _VIDEO_AD7179_H_ */ -- 2.7.4