From 86803008eabb8be14867ce2d41ef22e659a1a70c Mon Sep 17 00:00:00 2001 From: Ivan Kosarev Date: Fri, 20 May 2022 05:55:36 +0100 Subject: [PATCH] [MIR] Provide location of extra instruction operand when diagnosing it. Also resolves misspelled FileCheck directives caught with D125604. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D125965 --- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 2 +- llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir | 9 +++++---- llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir | 9 +++++---- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 52ba260..aed64d0 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1100,7 +1100,7 @@ bool MIParser::parse(MachineInstr *&MI) { if (!IsImplicitOp) { if (!MCID.isVariadic() && NumExplicitOps >= MCID.getNumOperands() && !Operand.Operand.isValidExcessOperand()) - return error("too many operands for instruction"); + return error(Operand.Begin, "too many operands for instruction"); ++NumExplicitOps; } diff --git a/llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir index db484f0..65cb32c 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir @@ -1,12 +1,13 @@ -# RUN: not llc -march=amdgcn -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass=none -o /dev/null %s 2>&1 | \ +# RUN: FileCheck --strict-whitespace %s --- name: extra_imm_operand body: | bb.0: - ; CHECK: [[@LINE+3]]:18: too many operands for instruction - ; CHECK-NEXT: S_ENDPGM 0, 0 - ; CHECK_NEXT: ^ + ; CHECK: [[@LINE+3]]:17: too many operands for instruction + ; CHECK-NEXT: {{^}} S_ENDPGM 0, 0 + ; CHECK-NEXT: {{^}} ^ S_ENDPGM 0, 0 ... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir index 03a6777..d6b2522 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir @@ -1,12 +1,13 @@ -# RUN: not llc -march=amdgcn -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass=none -o /dev/null %s 2>&1 | \ +# RUN: FileCheck --strict-whitespace %s --- name: extra_reg_operand body: | bb.0: - ; CHECK: [[@LINE+3]]:29: too many operands for instruction - ; S_ENDPGM 0, undef $vgpr0 - ; CHECK_NEXT: ^ + ; CHECK: [[@LINE+3]]:17: too many operands for instruction + ; CHECK-NEXT: {{^}} S_ENDPGM 0, undef $vgpr0 + ; CHECK-NEXT: {{^}} ^ S_ENDPGM 0, undef $vgpr0 ... -- 2.7.4