From 86693d485beaa373a62e2ce0261035b45ef8bcda Mon Sep 17 00:00:00 2001 From: uweigand Date: Tue, 4 Oct 2005 18:07:28 +0000 Subject: [PATCH] 2005-10-04 Adrian Straetling * config/s390/s390.md ("TDSI","DP"): New mode macros. ("TE","tg"): New mode attributes. ("sync_compare_and_swap"): Replace with a define_expand. ("sync_compare_and_swap_cc"): Replace GPR with TDSI. ("*sync_compare_and_swap_cc"): Replace with one pattern for dword_mode and one for GPRmode. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@104952 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 9 +++++++ gcc/config/s390/s390.md | 69 +++++++++++++++++++++++++++++++++++-------------- 2 files changed, 58 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c3723cd..f627c97 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2005-10-04 Adrian Straetling + + * config/s390/s390.md ("TDSI","DP"): New mode macros. + ("TE","tg"): New mode attributes. + ("sync_compare_and_swap"): Replace with a define_expand. + ("sync_compare_and_swap_cc"): Replace GPR with TDSI. + ("*sync_compare_and_swap_cc"): Replace with one pattern for + dword_mode and one for GPRmode. + 2005-10-04 Ian Lance Taylor PR preprocessor/13726 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 3f119c9..514b6a7 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -278,6 +278,10 @@ ;; same template. (define_mode_macro FPR [DF SF]) +;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated +;; from the same template. +(define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI]) + ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated ;; from the same template. (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) @@ -285,6 +289,7 @@ ;; This mode macro allows :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. +(define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) ;; This mode macro allows the QI and HI patterns to be defined from @@ -327,10 +332,18 @@ ;; in "RRE" for DImode and "RR" for SImode. (define_mode_attr E [(DI "E") (SI "")]) +;; This attribute handles differences in the instruction 'type' and will result +;; in "RSE" for TImode and "RS" for DImode. +(define_mode_attr TE [(TI "E") (DI "")]) + ;; In GPR templates, a string like "lcr" will expand to "lcgr" in DImode ;; and "lcr" in SImode. (define_mode_attr g [(DI "g") (SI "")]) +;; In DP templates, a string like "cds" will expand to "cdsg" in TImode +;; and "cds" in DImode. +(define_mode_attr tg [(TI "g") (DI "")]) + ;; In GPR templates, a string like "cdbr" will expand to "cgdbr" in DImode ;; and "cfdbr" in SImode. (define_mode_attr gf [(DI "g") (SI "f")]) @@ -7130,42 +7143,58 @@ ; compare and swap patterns. ; -(define_insn "sync_compare_and_swap" - [(set (match_operand:GPR 0 "register_operand" "=r") - (match_operand:GPR 1 "memory_operand" "+Q")) - (set (match_dup 1) - (unspec_volatile:GPR - [(match_dup 1) - (match_operand:GPR 2 "register_operand" "0") - (match_operand:GPR 3 "register_operand" "r")] - UNSPECV_CAS)) - (clobber (reg:CC CC_REGNUM))] - "" - "cs\t%0,%3,%S1" - [(set_attr "op_type" "RS") - (set_attr "type" "sem")]) +(define_expand "sync_compare_and_swap" + [(parallel + [(set (match_operand:TDSI 0 "register_operand" "") + (match_operand:TDSI 1 "memory_operand" "")) + (set (match_dup 1) + (unspec_volatile:TDSI + [(match_dup 1) + (match_operand:TDSI 2 "register_operand" "") + (match_operand:TDSI 3 "register_operand" "")] + UNSPECV_CAS)) + (set (reg:CCZ1 CC_REGNUM) + (compare:CCZ1 (match_dup 1) (match_dup 2)))])] + "") (define_expand "sync_compare_and_swap_cc" [(parallel - [(set (match_operand:GPR 0 "register_operand" "") - (match_operand:GPR 1 "memory_operand" "")) + [(set (match_operand:TDSI 0 "register_operand" "") + (match_operand:TDSI 1 "memory_operand" "")) (set (match_dup 1) - (unspec_volatile:GPR + (unspec_volatile:TDSI [(match_dup 1) - (match_operand:GPR 2 "register_operand" "") - (match_operand:GPR 3 "register_operand" "")] + (match_operand:TDSI 2 "register_operand" "") + (match_operand:TDSI 3 "register_operand" "")] UNSPECV_CAS)) (set (match_dup 4) (compare:CCZ1 (match_dup 1) (match_dup 2)))])] "" { + /* Emulate compare. */ operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); s390_compare_op0 = operands[1]; s390_compare_op1 = operands[2]; s390_compare_emitted = operands[4]; }) -(define_insn "*sync_compare_and_swap_cc" +(define_insn "*sync_compare_and_swap" + [(set (match_operand:DP 0 "register_operand" "=r") + (match_operand:DP 1 "memory_operand" "+Q")) + (set (match_dup 1) + (unspec_volatile:DP + [(match_dup 1) + (match_operand:DP 2 "register_operand" "0") + (match_operand:DP 3 "register_operand" "r")] + UNSPECV_CAS)) + (set (reg:CCZ1 CC_REGNUM) + (compare:CCZ1 (match_dup 1) (match_dup 2)))] + "" + "cds\t%0,%3,%S1" + [(set_attr "op_type" "RS") + (set_attr "type" "sem")]) + +(define_insn "*sync_compare_and_swap" [(set (match_operand:GPR 0 "register_operand" "=r") (match_operand:GPR 1 "memory_operand" "+Q")) (set (match_dup 1) -- 2.7.4