From 862f87de00a9695a00c2ed05d7a9c543323bba9c Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 24 May 2016 13:41:01 -0400 Subject: [PATCH] clk: exynos5420: Set ID for aclk333 gate clock The aclk333 clock needs to be ungated during the MFC power domain switch, so set the clock ID to allow the Exynos power domain logic to lookup this clock if is defined in the MFC PD device tree node. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki [backport of mainline commit 34cba900375ec1751a87d3655ad03b9a5b022362] Signed-off-by: Marek Szyprowski Change-Id: I34cba900375ec1751a87d3655ad03b9a5b022362 --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f87660806555..c89c9b2247fc 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -930,7 +930,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { GATE_BUS_TOP, 13, 0, 0), GATE(0, "aclk166", "mout_user_aclk166", GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), - GATE(0, "aclk333", "mout_user_aclk333", + GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), -- 2.34.1