From 860b4479dccad323ae22361294e69765c3fdd25f Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 11 Oct 2021 21:51:45 +0100 Subject: [PATCH] [ARM] Be more explicit about disabling CombineBaseUpdate for MVE. This shouldn't be called for non-neon targets at the moment in either case, but it is good to be expliit about the CombineBaseUpdate being a NEON function, not expecting to be run under MVE. --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 51ba354..94605f8 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -15781,11 +15781,12 @@ static SDValue PerformVDUPCombine(SDNode *N, SelectionDAG &DAG, } static SDValue PerformLOADCombine(SDNode *N, - TargetLowering::DAGCombinerInfo &DCI) { + TargetLowering::DAGCombinerInfo &DCI, + const ARMSubtarget *Subtarget) { EVT VT = N->getValueType(0); // If this is a legal vector load, try to combine it into a VLD1_UPD. - if (ISD::isNormalLoad(N) && VT.isVector() && + if (Subtarget->hasNEON() && ISD::isNormalLoad(N) && VT.isVector() && DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) return CombineBaseUpdate(N, DCI); @@ -17999,9 +18000,12 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, case ISD::SMAX: case ISD::UMAX: return PerformMinMaxCombine(N, DCI.DAG, Subtarget); - case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); - case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG); - case ISD::LOAD: return PerformLOADCombine(N, DCI); + case ARMISD::CMOV: + return PerformCMOVCombine(N, DCI.DAG); + case ARMISD::BRCOND: + return PerformBRCONDCombine(N, DCI.DAG); + case ISD::LOAD: + return PerformLOADCombine(N, DCI, Subtarget); case ARMISD::VLD1DUP: case ARMISD::VLD2DUP: case ARMISD::VLD3DUP: -- 2.7.4