From 85ef4a1c472f20b34edc1959c9ba5ce46eede784 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Fri, 16 Sep 2016 15:12:46 +0000
Subject: [PATCH] [AArch64][GlobalISel] Add default regbank mapping for
 int<>FP.

llvm-svn: 281739
---
 .../AArch64/AArch64RegisterBankInfo.cpp       | 10 +++
 .../GlobalISel/regbankselect-default.mir      | 81 +++++++++++++++++++
 2 files changed, 91 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index dab6225e4cfa..e0058af4c3ee 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -224,6 +224,16 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   // Some of the floating-point instructions have mixed GPR and FPR operands:
   // fine-tune the computed mapping.
   switch (Opc) {
+  case TargetOpcode::G_SITOFP:
+  case TargetOpcode::G_UITOFP: {
+    OpBanks = {AArch64::FPRRegBankID, AArch64::GPRRegBankID};
+    break;
+  }
+  case TargetOpcode::G_FPTOSI:
+  case TargetOpcode::G_FPTOUI: {
+    OpBanks = {AArch64::GPRRegBankID, AArch64::FPRRegBankID};
+    break;
+  }
   case TargetOpcode::G_FCMP: {
     OpBanks = {AArch64::GPRRegBankID, /* Predicate */ 0, AArch64::FPRRegBankID,
                AArch64::FPRRegBankID};
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 740223d5468b..12162eb54a83 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -61,6 +61,11 @@
 
   define void @test_fcmp_s32() { ret void }
 
+  define void @test_sitofp_s64_s32() { ret void }
+  define void @test_uitofp_s32_s64() { ret void }
+
+  define void @test_fptosi_s64_s32() { ret void }
+  define void @test_fptoui_s32_s64() { ret void }
 ...
 
 ---
@@ -787,3 +792,79 @@ body: |
     %0(s32) = COPY %s0
     %1(s1) = G_FCMP floatpred(olt), %0, %0
 ...
+
+---
+# CHECK-LABEL: name: test_sitofp_s64_s32
+name:            test_sitofp_s64_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: gpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %w0
+    ; CHECK:      %0(s32) = COPY %w0
+    ; CHECK:      %1(s64) = G_SITOFP %0
+    %0(s32) = COPY %w0
+    %1(s64) = G_SITOFP %0
+...
+
+---
+# CHECK-LABEL: name: test_uitofp_s32_s64
+name:            test_uitofp_s32_s64
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: gpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %x0
+    ; CHECK:      %0(s64) = COPY %x0
+    ; CHECK:      %1(s32) = G_UITOFP %0
+    %0(s64) = COPY %x0
+    %1(s32) = G_UITOFP %0
+...
+
+---
+# CHECK-LABEL: name: test_fptosi_s64_s32
+name:            test_fptosi_s64_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s64) = G_FPTOSI %0
+    %0(s32) = COPY %s0
+    %1(s64) = G_FPTOSI %0
+...
+
+---
+# CHECK-LABEL: name: test_fptoui_s32_s64
+name:            test_fptoui_s32_s64
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %d0
+    ; CHECK:      %0(s64) = COPY %d0
+    ; CHECK:      %1(s32) = G_FPTOUI %0
+    %0(s64) = COPY %d0
+    %1(s32) = G_FPTOUI %0
+...
-- 
2.34.1