From 858451c50b81379d1761e3f31d8c5e712b6fb77f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 12 Mar 2023 11:14:20 -0700 Subject: [PATCH] [RISCV] Add test cases for fli.h and fli.d CodeGen bugs. NFC We fail to use fli.h for the 2 denormal values. We use fli.d for some values where the value is larger than a float can represent due to truncating the exponent to 8 bits without checking if it fits in 8 bits. --- llvm/test/CodeGen/RISCV/double-zfa.ll | 10 ++++++++++ llvm/test/CodeGen/RISCV/half-zfa-fli.ll | 34 +++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/double-zfa.ll b/llvm/test/CodeGen/RISCV/double-zfa.ll index eb077b3..427c5b5 100644 --- a/llvm/test/CodeGen/RISCV/double-zfa.ll +++ b/llvm/test/CodeGen/RISCV/double-zfa.ll @@ -77,6 +77,16 @@ define double @loadfpimm9() { ret double 255.0 } +; Negative test. This is 1 * 2^256. +; FIXME: This should not use fli.d +define double @loadfpimm10() { +; CHECK-LABEL: loadfpimm10: +; CHECK: # %bb.0: +; CHECK-NEXT: fli.d fa0, 2.0 +; CHECK-NEXT: ret + ret double 0x1000000000000000 +} + declare double @llvm.minimum.f64(double, double) define double @fminm_d(double %a, double %b) nounwind { diff --git a/llvm/test/CodeGen/RISCV/half-zfa-fli.ll b/llvm/test/CodeGen/RISCV/half-zfa-fli.ll index 36c49da..500c74c 100644 --- a/llvm/test/CodeGen/RISCV/half-zfa-fli.ll +++ b/llvm/test/CodeGen/RISCV/half-zfa-fli.ll @@ -134,3 +134,37 @@ define half @loadfpimm9() { ; ZFHMIN-NEXT: ret ret half 255.0 } + +; This is 1 * 2^-16 +; FIXME: this should use fli.h +define half @loadfpimm10() { +; CHECK-LABEL: loadfpimm10: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 256 +; CHECK-NEXT: fmv.h.x fa0, a0 +; CHECK-NEXT: ret +; +; ZFHMIN-LABEL: loadfpimm10: +; ZFHMIN: # %bb.0: +; ZFHMIN-NEXT: li a0, 256 +; ZFHMIN-NEXT: fmv.h.x fa0, a0 +; ZFHMIN-NEXT: ret + ret half 0xH0100 +} + +; This is 1 * 2^-15 +; FIXME: This should use fli.h +define half @loadfpimm11() { +; CHECK-LABEL: loadfpimm11: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 512 +; CHECK-NEXT: fmv.h.x fa0, a0 +; CHECK-NEXT: ret +; +; ZFHMIN-LABEL: loadfpimm11: +; ZFHMIN: # %bb.0: +; ZFHMIN-NEXT: li a0, 512 +; ZFHMIN-NEXT: fmv.h.x fa0, a0 +; ZFHMIN-NEXT: ret + ret half 0xH0200 +} -- 2.7.4