From 8550509b64e671e4ead8dbc0628c54b5f856875f Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Thu, 28 Jul 2016 17:15:15 +0000
Subject: [PATCH] [AArch64][GlobalISel] Select G_BR.

This is the first unsized instruction we support; move down the
'sized' check to binops.

llvm-svn: 277007
---
 .../Target/AArch64/AArch64InstructionSelector.cpp   | 21 +++++++++++++--------
 .../AArch64/GlobalISel/arm64-instructionselect.mir  | 18 ++++++++++++++++++
 2 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 716f79e..492024e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -102,22 +102,27 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
   LLT Ty = I.getType();
   assert(Ty.isValid() && "Generic instruction doesn't have a type");
 
-  // FIXME: Support unsized instructions (e.g., G_BR).
-  if (!Ty.isSized()) {
-    DEBUG(dbgs() << "Unsized generic instructions are unsupported\n");
-    return false;
+  switch (I.getOpcode()) {
+  case TargetOpcode::G_BR: {
+    I.setDesc(TII.get(AArch64::B));
+    I.removeTypes();
+    return true;
   }
 
-  // The size (in bits) of the operation, or 0 for the label type.
-  const unsigned OpSize = Ty.getSizeInBits();
-
-  switch (I.getOpcode()) {
   case TargetOpcode::G_OR:
   case TargetOpcode::G_AND:
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB: {
     DEBUG(dbgs() << "AArch64: Selecting: binop\n");
 
+    if (!Ty.isSized()) {
+      DEBUG(dbgs() << "Generic binop should be sized\n");
+      return false;
+    }
+
+    // The size (in bits) of the operation, or 0 for the label type.
+    const unsigned OpSize = Ty.getSizeInBits();
+
     // Reject the various things we don't support yet.
     {
       const RegisterBank *PrevOpBank = nullptr;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index 2924b54..555956c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -20,6 +20,8 @@
   define void @and_s32_gpr() { ret void }
   define void @and_s64_gpr() { ret void }
 
+  define void @unconditional_br() { ret void }
+
 ...
 
 ---
@@ -214,3 +216,19 @@ body:             |
     %0(64) = COPY %x0
     %1(64) = G_AND s64 %0, %0
 ...
+
+---
+# CHECK-LABEL: name: unconditional_br
+name:            unconditional_br
+isSSA:           true
+
+# CHECK:  body:
+# CHECK:   bb.0:
+# CHECK:    successors: %bb.0
+# CHECK:    B %bb.0
+body:             |
+  bb.0:
+    successors: %bb.0
+
+    G_BR unsized %bb.0
+...
-- 
2.7.4