From 854de7c4d074f1c5d10be08809fa631e53b168b0 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Mon, 22 Mar 2021 10:39:02 -0700 Subject: [PATCH] [tests] Refresh a bunch of autogen test to adjust for format changes --- llvm/test/Transforms/GVN/loadpre-context.ll | 6 +++--- llvm/test/Transforms/InstCombine/select.ll | 2 +- llvm/test/Transforms/MemCpyOpt/memcpy.ll | 11 +++++------ llvm/test/Transforms/MemCpyOpt/sret.ll | 2 +- llvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll | 4 ++-- llvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll | 8 ++++---- llvm/test/Transforms/MergeICmps/X86/pr41917.ll | 4 ++-- llvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll | 6 +++--- 8 files changed, 21 insertions(+), 22 deletions(-) diff --git a/llvm/test/Transforms/GVN/loadpre-context.ll b/llvm/test/Transforms/GVN/loadpre-context.ll index 50a43b0..1a178e7 100644 --- a/llvm/test/Transforms/GVN/loadpre-context.ll +++ b/llvm/test/Transforms/GVN/loadpre-context.ll @@ -14,7 +14,7 @@ define i32 @loadpre_critical_edge(i32* align 8 dereferenceable_or_null(48) %arg, ; CHECK: header: ; CHECK-NEXT: [[V:%.*]] = phi i32 [ [[V_PRE]], [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[SUM:%.*]], [[HEADER]] ] ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[IV_NEXT:%.*]], [[HEADER]] ] -; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) +; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) #[[ATTR0:[0-9]+]] ; CHECK-NEXT: [[SUM]] = add i32 [[NEW_V]], [[V]] ; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 @@ -59,7 +59,7 @@ define i32 @loadpre_basic(i32* align 8 dereferenceable_or_null(48) %arg, i32 %N) ; CHECK: header: ; CHECK-NEXT: [[V:%.*]] = phi i32 [ [[V_PRE]], [[PREHEADER]] ], [ [[SUM:%.*]], [[HEADER]] ] ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[PREHEADER]] ], [ [[IV_NEXT:%.*]], [[HEADER]] ] -; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) +; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) #[[ATTR0]] ; CHECK-NEXT: [[SUM]] = add i32 [[NEW_V]], [[V]] ; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 @@ -107,7 +107,7 @@ define i32 @loadpre_maybe_null(i32* align 8 dereferenceable_or_null(48) %arg, i3 ; CHECK-NEXT: br label [[HEADER:%.*]] ; CHECK: header: ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[PREHEADER]] ], [ [[IV_NEXT:%.*]], [[HEADER]] ] -; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) +; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) #[[ATTR0]] ; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[ARG]], align 4 ; CHECK-NEXT: [[SUM:%.*]] = add i32 [[NEW_V]], [[V]] ; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4 diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll index d603de3..ad1d329 100644 --- a/llvm/test/Transforms/InstCombine/select.ll +++ b/llvm/test/Transforms/InstCombine/select.ll @@ -2680,7 +2680,7 @@ define void @select_freeze_icmp_multuses(i32 %x, i32 %y) { define i32 @pr47322_more_poisonous_replacement(i32 %arg) { ; CHECK-LABEL: @pr47322_more_poisonous_replacement( ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0 -; CHECK-NEXT: [[TRAILING:%.*]] = call i32 @llvm.cttz.i32(i32 [[ARG]], i1 immarg true), [[RNG0:!range !.*]] +; CHECK-NEXT: [[TRAILING:%.*]] = call i32 @llvm.cttz.i32(i32 [[ARG]], i1 immarg true), !range [[RNG0:![0-9]+]] ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[ARG]], [[TRAILING]] ; CHECK-NEXT: [[R1_SROA_0_1:%.*]] = select i1 [[CMP]], i32 0, i32 [[SHIFTED]] ; CHECK-NEXT: ret i32 [[R1_SROA_0_1]] diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy.ll b/llvm/test/Transforms/MemCpyOpt/memcpy.ll index 096d5d9..96f4faa 100644 --- a/llvm/test/Transforms/MemCpyOpt/memcpy.ll +++ b/llvm/test/Transforms/MemCpyOpt/memcpy.ll @@ -14,7 +14,7 @@ define void @test1(%0* sret(%0) %agg.result, x86_fp80 %z.0, x86_fp80 %z.1) noun ; CHECK-NEXT: [[TMP2:%.*]] = alloca [[TMP0:%.*]], align 16 ; CHECK-NEXT: [[MEMTMP:%.*]] = alloca [[TMP0]], align 16 ; CHECK-NEXT: [[TMP5:%.*]] = fsub x86_fp80 0xK80000000000000000000, [[Z_1:%.*]] -; CHECK-NEXT: call void @ccoshl(%0* sret(%0) [[TMP2]], x86_fp80 [[TMP5]], x86_fp80 [[Z_0:%.*]]) [[ATTR0:#.*]] +; CHECK-NEXT: call void @ccoshl(%0* sret([[TMP0]]) [[TMP2]], x86_fp80 [[TMP5]], x86_fp80 [[Z_0:%.*]]) #[[ATTR0:[0-9]+]] ; CHECK-NEXT: [[TMP219:%.*]] = bitcast %0* [[TMP2]] to i8* ; CHECK-NEXT: [[MEMTMP20:%.*]] = bitcast %0* [[MEMTMP]] to i8* ; CHECK-NEXT: [[AGG_RESULT21:%.*]] = bitcast %0* [[AGG_RESULT:%.*]] to i8* @@ -222,7 +222,7 @@ define i32 @test5(i32 %x) nounwind ssp { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP]], i8* align 16 bitcast (%struct.S* @sS to i8*), i64 32, i1 false) ; CHECK-NEXT: [[A:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[Y]], i64 0, i32 1, i64 0 ; CHECK-NEXT: store i8 4, i8* [[A]], align 1 -; CHECK-NEXT: call void @test5a(%struct.S* byval(%struct.S) align 16 [[Y]]) +; CHECK-NEXT: call void @test5a(%struct.S* byval([[STRUCT_S]]) align 16 [[Y]]) ; CHECK-NEXT: ret i32 0 ; entry: @@ -252,7 +252,7 @@ define void @test6(i8 *%P) { define i32 @test7(%struct.p* nocapture align 8 byval(%struct.p) %q) nounwind ssp { ; CHECK-LABEL: @test7( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32 @g(%struct.p* byval(%struct.p) align 8 [[Q:%.*]]) [[ATTR0]] +; CHECK-NEXT: [[CALL:%.*]] = call i32 @g(%struct.p* byval([[STRUCT_P:%.*]]) align 8 [[Q:%.*]]) #[[ATTR0]] ; CHECK-NEXT: ret i32 [[CALL]] ; entry: @@ -295,7 +295,7 @@ define void @test9_addrspacecast() nounwind ssp uwtable { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_BIG:%.*]], align 4 ; CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_BIG]], align 4 -; CHECK-NEXT: call void @f1(%struct.big* sret(%struct.big) [[B]]) +; CHECK-NEXT: call void @f1(%struct.big* sret([[STRUCT_BIG]]) [[B]]) ; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast %struct.big* [[B]] to i8 addrspace(1)* ; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast %struct.big* [[TMP]] to i8 addrspace(1)* ; CHECK-NEXT: call void @f2(%struct.big* [[B]]) @@ -317,7 +317,7 @@ define void @test9() nounwind ssp uwtable { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_BIG:%.*]], align 4 ; CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_BIG]], align 4 -; CHECK-NEXT: call void @f1(%struct.big* sret(%struct.big) [[B]]) +; CHECK-NEXT: call void @f1(%struct.big* sret([[STRUCT_BIG]]) [[B]]) ; CHECK-NEXT: [[TMP0:%.*]] = bitcast %struct.big* [[B]] to i8* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %struct.big* [[TMP]] to i8* ; CHECK-NEXT: call void @f2(%struct.big* [[B]]) @@ -381,7 +381,6 @@ declare void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* nocapture, i8* nocaptur declare void @f1(%struct.big* nocapture sret(%struct.big)) declare void @f2(%struct.big*) -; CHECK: attributes [[ATTR0]] = { nounwind } ; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #2 = { nounwind ssp } ; CHECK: attributes #3 = { willreturn } diff --git a/llvm/test/Transforms/MemCpyOpt/sret.ll b/llvm/test/Transforms/MemCpyOpt/sret.ll index 12608ed..98f22ed 100644 --- a/llvm/test/Transforms/MemCpyOpt/sret.ll +++ b/llvm/test/Transforms/MemCpyOpt/sret.ll @@ -21,7 +21,7 @@ define void @ccosl(%0* noalias sret(%0) %agg.result, %0* byval(%0) align 8 %z) n ; CHECK-NEXT: [[TMP8:%.*]] = load x86_fp80, x86_fp80* [[TMP7]], align 16 ; CHECK-NEXT: store x86_fp80 [[TMP3]], x86_fp80* [[REAL]], align 16 ; CHECK-NEXT: store x86_fp80 [[TMP8]], x86_fp80* [[TMP4]], align 16 -; CHECK-NEXT: call void @ccoshl(%0* noalias sret(%0) [[AGG_RESULT:%.*]], %0* byval(%0) align 8 [[IZ]]) [[ATTR0:#.*]] +; CHECK-NEXT: call void @ccoshl(%0* noalias sret([[TMP0]]) [[AGG_RESULT:%.*]], %0* byval([[TMP0]]) align 8 [[IZ]]) #[[ATTR0:[0-9]+]] ; CHECK-NEXT: [[MEMTMP14:%.*]] = bitcast %0* [[MEMTMP]] to i8* ; CHECK-NEXT: [[AGG_RESULT15:%.*]] = bitcast %0* [[AGG_RESULT]] to i8* ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll b/llvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll index 3bc9f83..25a73fa 100644 --- a/llvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll +++ b/llvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll @@ -6,8 +6,8 @@ define zeroext i1 @opeq1( ; X86-LABEL: @opeq1( ; X86-NEXT: "entry+land.rhs.i+land.rhs.i.2+land.rhs.i.3": -; X86-NEXT: [[PTR:%.*]] = alloca i32 -; X86-NEXT: store i32 42, i32* [[PTR]] +; X86-NEXT: [[PTR:%.*]] = alloca i32, align 4 +; X86-NEXT: store i32 42, i32* [[PTR]], align 4 ; X86-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[S:%.*]], %S* [[A:%.*]], i64 0, i32 0 ; X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[S]], %S* [[B:%.*]], i64 0, i32 0 ; X86-NEXT: [[CSTR:%.*]] = bitcast i32* [[TMP0]] to i8* diff --git a/llvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll b/llvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll index c15fd88..7a5a6e4 100644 --- a/llvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll +++ b/llvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll @@ -20,15 +20,15 @@ define zeroext i1 @opeq1( ; CHECK: entry2: ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[S]], %S* [[A]], i64 0, i32 3 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[S]], %S* [[B]], i64 0, i32 2 -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP4]], align 4 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP5]], [[TMP6]] ; CHECK-NEXT: br i1 [[TMP7]], label [[LAND_RHS_I_31:%.*]], label [[OPEQ1_EXIT]] ; CHECK: land.rhs.i.31: ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[S]], %S* [[A]], i64 0, i32 3 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[S]], %S* [[B]], i64 0, i32 3 -; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP8]] -; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 4 +; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 4 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], [[TMP11]] ; CHECK-NEXT: br label [[OPEQ1_EXIT]] ; CHECK: opeq1.exit: diff --git a/llvm/test/Transforms/MergeICmps/X86/pr41917.ll b/llvm/test/Transforms/MergeICmps/X86/pr41917.ll index 22cba94..0af00c7 100644 --- a/llvm/test/Transforms/MergeICmps/X86/pr41917.ll +++ b/llvm/test/Transforms/MergeICmps/X86/pr41917.ll @@ -10,10 +10,10 @@ target triple = "i386-pc-windows-msvc19.11.0" define dso_local zeroext i1 @pr41917(%class.a* byval(%class.a) nocapture readonly align 4 %g, %class.a* byval(%class.a) nocapture readonly align 4 %p2) local_unnamed_addr #0 { ; CHECK-LABEL: @pr41917( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i1 @f2() #3 +; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i1 @f2() #[[ATTR3:[0-9]+]] ; CHECK-NEXT: br i1 [[CALL]], label [[LAND_RHS:%.*]], label %"land.end+land.rhs3" ; CHECK: land.rhs: -; CHECK-NEXT: [[CALL1:%.*]] = tail call zeroext i1 @f2() #3 +; CHECK-NEXT: [[CALL1:%.*]] = tail call zeroext i1 @f2() #[[ATTR3]] ; CHECK-NEXT: br label %"land.end+land.rhs3" ; CHECK: "land.end+land.rhs3": ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_A:%.*]], %class.a* [[G:%.*]], i32 0, i32 1 diff --git a/llvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll b/llvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll index 78b4f45..bcac5f9 100644 --- a/llvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll +++ b/llvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll @@ -72,10 +72,10 @@ define i8* @test4(i1* %dummy, i8* %a, i8* %b) { ; expressions. ; CHECK-LABEL: @test4( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[COND1:%.*]] = load volatile i1, i1* [[DUMMY:%.*]] +; CHECK-NEXT: [[COND1:%.*]] = load volatile i1, i1* [[DUMMY:%.*]], align 1 ; CHECK-NEXT: br i1 [[COND1]], label [[IF:%.*]], label [[END:%.*]] ; CHECK: if: -; CHECK-NEXT: [[COND2:%.*]] = load volatile i1, i1* [[DUMMY]] +; CHECK-NEXT: [[COND2:%.*]] = load volatile i1, i1* [[DUMMY]], align 1 ; CHECK-NEXT: br i1 [[COND2]], label [[THEN:%.*]], label [[END]] ; CHECK: then: ; CHECK-NEXT: br label [[END]] @@ -126,7 +126,7 @@ define i32* @test5(i32 %a, i32 %b, i32 %c, i32* dereferenceable(10) %ptr1, i32* ; CHECK-NEXT: br i1 [[T1]], label [[BB1:%.*]], label [[BB3:%.*]] ; CHECK: bb1: ; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[C:%.*]], 1 -; CHECK-NEXT: [[T3:%.*]] = load i32*, i32** [[PTR3:%.*]] +; CHECK-NEXT: [[T3:%.*]] = load i32*, i32** [[PTR3:%.*]], align 8 ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[T2]], i32* [[T3]], i32* [[PTR2:%.*]] ; CHECK-NEXT: ret i32* [[SPEC_SELECT]] ; CHECK: bb3: -- 2.7.4