From 8509ebb68a022bd1b0629c3362638d217ad0c477 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 22 Jun 2023 12:50:43 +0300 Subject: [PATCH] anv: align buffers to a cache line Signed-off-by: Lionel Landwerlin Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9217 Reviewed-by: Yiwei Zhang Part-of: --- src/intel/vulkan/anv_device.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 8f52a4b..c33bc63 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -4353,11 +4353,11 @@ anv_get_buffer_memory_requirements(struct anv_device *device, */ uint32_t memory_types = (1ull << device->physical->memory.type_count) - 1; - /* Base alignment requirement of a cache line */ - uint32_t alignment = 16; - - if (usage & VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT) - alignment = MAX2(alignment, ANV_UBO_ALIGNMENT); + /* The GPU appears to write back to main memory in cachelines. Writes to a + * buffers should not clobber with writes to another buffers so make sure + * those are in different cachelines. + */ + uint32_t alignment = 64; pMemoryRequirements->memoryRequirements.size = size; pMemoryRequirements->memoryRequirements.alignment = alignment; -- 2.7.4