From 84e83b54bd79734dfac5a74436f4dd80e4a34146 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 13 Nov 2019 12:09:34 -0800 Subject: [PATCH] [TargetLowering] Increase the storage size of NumRegistersForVT to allow the type break down for v256i1 and other types to be stored correctly v256i1 on X86 without avx512 breaks down to 256 i8 values when passed between basic blocks. But the NumRegistersForVT was sized at a byte for each VT. This results in 256 being stored as 0. This patch enlarges the type to 16 bits and adds an assert to ensure that no information is lost when the entry is stored. Differential Revision: https://reviews.llvm.org/D70138 --- llvm/include/llvm/CodeGen/TargetLowering.h | 2 +- llvm/lib/CodeGen/TargetLoweringBase.cpp | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index d0706c2320ec..2a7a6ce6961a 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -2741,7 +2741,7 @@ private: /// This indicates the default register class to use for each ValueType the /// target supports natively. const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; - unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; + uint16_t NumRegistersForVT[MVT::LAST_VALUETYPE]; MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; /// This indicates the "representative" register class to use for each diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index c5b129029493..7f3eb4107ffe 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1332,8 +1332,11 @@ void TargetLoweringBase::computeRegisterProperties( MVT IntermediateVT; MVT RegisterVT; unsigned NumIntermediates; - NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, + unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, RegisterVT, this); + NumRegistersForVT[i] = NumRegisters; + assert(NumRegistersForVT[i] == NumRegisters && + "NumRegistersForVT size cannot represent NumRegisters!"); RegisterTypeForVT[i] = RegisterVT; MVT NVT = VT.getPow2VectorType(); -- 2.34.1