From 84b4b2a8aacf6655d3f2a9f03dec3913a00aabdb Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 29 Jan 2012 04:17:30 +0100 Subject: [PATCH] r600g: don't use register mask for CB_COLOR_CONTROL on r6xx-r7xx Reviewed-by: Dave Airlie Reviewed-by: Alex Deucher --- src/gallium/drivers/r600/r600_pipe.h | 2 ++ src/gallium/drivers/r600/r600_state.c | 8 +------- src/gallium/drivers/r600/r600_state_common.c | 14 ++++++++++++++ 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 169d581..b7c5e55 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -116,6 +116,7 @@ struct r600_pipe_rasterizer { struct r600_pipe_blend { struct r600_pipe_state rstate; unsigned cb_target_mask; + unsigned cb_color_control; }; struct r600_pipe_dsa { @@ -207,6 +208,7 @@ struct r600_pipe_context { struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; struct pipe_framebuffer_state framebuffer; unsigned cb_target_mask; + unsigned cb_color_control; /* for saving when using blitter */ struct pipe_stencil_ref stencil_ref; struct pipe_viewport_state viewport; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 821da0d..e1d8ab3 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -810,9 +810,7 @@ static void *r600_create_blend_state(struct pipe_context *ctx, } } blend->cb_target_mask = target_mask; - /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */ - r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, - color_control, 0xFFFFFFFD, NULL, 0); + blend->cb_color_control = color_control; for (int i = 0; i < 8; i++) { /* state->rt entries > 0 only written if independent blending */ @@ -2166,10 +2164,6 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad r600_pipe_state_add_reg(rstate, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0x00000000, 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, - S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all), - S_028808_MULTIWRITE_ENABLE(1), - NULL, 0); /* only set some bits here, the other bits are set in the dsa state */ r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 8bf5513..9833de0 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -73,6 +73,11 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state) rstate = &blend->rstate; rctx->states[rstate->id] = rstate; rctx->cb_target_mask = blend->cb_target_mask; + + /* Replace every bit except MULTIWRITE_ENABLE. */ + rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE; + rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE; + r600_context_pipe_state_set(&rctx->ctx, rstate); } @@ -326,6 +331,9 @@ void r600_bind_ps_shader(struct pipe_context *ctx, void *state) rctx->ps_shader = (struct r600_pipe_shader *)state; if (state) { r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate); + + rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE; + rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all); } if (rctx->ps_shader && rctx->vs_shader) { r600_adjust_gprs(rctx); @@ -750,6 +758,8 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, S_028814_PROVOKING_VTX_LAST(1), NULL, 0); + if (rctx->chip_class <= R700) + r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, 0xFFFFFFFF, NULL, 0); } rctx->vgt.nregs = 0; @@ -771,7 +781,11 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) { r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1)); + } else { + r600_pipe_state_mod_reg(&rctx->vgt, 0); } + if (rctx->chip_class <= R700) + r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control); r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt); -- 2.7.4