From 84404f30b311e7943ff4997a11fb0602207392fc Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Mon, 28 Nov 2016 14:01:51 +0000 Subject: [PATCH] [SystemZ] Support execution hint instructions This adds assembler support for the instructions provided by the execution-hint facility (NIAI and BP(R)P). This required adding support for the new relocation types for 12-bit and 24-bit PC- relative offsets used by the BP(R)P instructions. llvm-svn: 288031 --- llvm/include/llvm/Support/ELFRelocs/SystemZ.def | 4 + .../Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 6 + .../SystemZ/Disassembler/SystemZDisassembler.cpp | 12 ++ .../SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp | 4 + .../SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp | 18 +++ .../Target/SystemZ/MCTargetDesc/SystemZMCFixups.h | 4 +- .../SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp | 4 + llvm/lib/Target/SystemZ/SystemZFeatures.td | 6 + llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 65 +++++++++++ llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 11 +- llvm/lib/Target/SystemZ/SystemZOperands.td | 16 +++ llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 5 +- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 4 +- llvm/lib/Target/SystemZ/SystemZSubtarget.cpp | 5 +- llvm/lib/Target/SystemZ/SystemZSubtarget.h | 4 + llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt | 64 +++++++++++ llvm/test/MC/Disassembler/SystemZ/insns.txt | 12 ++ llvm/test/MC/SystemZ/fixups-zEC12.s | 34 ++++++ llvm/test/MC/SystemZ/insn-bad-z196.s | 15 +++ llvm/test/MC/SystemZ/insn-bad-zEC12.s | 72 ++++++++++++ llvm/test/MC/SystemZ/insn-good-zEC12.s | 122 +++++++++++++++++++++ 21 files changed, 481 insertions(+), 6 deletions(-) create mode 100644 llvm/test/MC/SystemZ/fixups-zEC12.s diff --git a/llvm/include/llvm/Support/ELFRelocs/SystemZ.def b/llvm/include/llvm/Support/ELFRelocs/SystemZ.def index 711f940..d6c0b79 100644 --- a/llvm/include/llvm/Support/ELFRelocs/SystemZ.def +++ b/llvm/include/llvm/Support/ELFRelocs/SystemZ.def @@ -65,3 +65,7 @@ ELF_RELOC(R_390_GOT20, 58) ELF_RELOC(R_390_GOTPLT20, 59) ELF_RELOC(R_390_TLS_GOTIE20, 60) ELF_RELOC(R_390_IRELATIVE, 61) +ELF_RELOC(R_390_PC12DBL, 62) +ELF_RELOC(R_390_PLT12DBL, 63) +ELF_RELOC(R_390_PC24DBL, 64) +ELF_RELOC(R_390_PLT24DBL, 65) diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index 3f373de..a94717c 100644 --- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -484,9 +484,15 @@ public: OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg); } + OperandMatchResultTy parsePCRel12(OperandVector &Operands) { + return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false); + } OperandMatchResultTy parsePCRel16(OperandVector &Operands) { return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); } + OperandMatchResultTy parsePCRel24(OperandVector &Operands) { + return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false); + } OperandMatchResultTy parsePCRel32(OperandVector &Operands) { return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false); } diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index a1b8422..1806e015 100644 --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -247,12 +247,24 @@ static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) { + return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder); +} + static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder); } +static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) { + return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder); +} + static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp index d1aad2b..5a34095 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -25,7 +25,9 @@ static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value) { return Value; switch (unsigned(Kind)) { + case SystemZ::FK_390_PC12DBL: case SystemZ::FK_390_PC16DBL: + case SystemZ::FK_390_PC24DBL: case SystemZ::FK_390_PC32DBL: return (int64_t)Value / 2; @@ -72,7 +74,9 @@ public: const MCFixupKindInfo & SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = { + { "FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel }, { "FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, { "FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "FK_390_TLS_CALL", 0, 0, 0 } }; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index ec82c9c..7082aba 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -113,6 +113,24 @@ private: return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2, true); } + uint64_t getPC12DBLBPPEncoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + return getPCRelEncoding(MI, OpNum, Fixups, + SystemZ::FK_390_PC12DBL, 1, false); + } + uint64_t getPC16DBLBPPEncoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + return getPCRelEncoding(MI, OpNum, Fixups, + SystemZ::FK_390_PC16DBL, 4, false); + } + uint64_t getPC24DBLBPPEncoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + return getPCRelEncoding(MI, OpNum, Fixups, + SystemZ::FK_390_PC24DBL, 3, false); + } private: uint64_t computeAvailableFeatures(const FeatureBitset &FB) const; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h index 229ab5d..c012acc 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h @@ -16,7 +16,9 @@ namespace llvm { namespace SystemZ { enum FixupKind { // These correspond directly to R_390_* relocations. - FK_390_PC16DBL = FirstTargetFixupKind, + FK_390_PC12DBL = FirstTargetFixupKind, + FK_390_PC16DBL, + FK_390_PC24DBL, FK_390_PC32DBL, FK_390_TLS_CALL, diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp index 368c95f..43a96e8 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp @@ -53,7 +53,9 @@ static unsigned getPCRelReloc(unsigned Kind) { case FK_Data_2: return ELF::R_390_PC16; case FK_Data_4: return ELF::R_390_PC32; case FK_Data_8: return ELF::R_390_PC64; + case SystemZ::FK_390_PC12DBL: return ELF::R_390_PC12DBL; case SystemZ::FK_390_PC16DBL: return ELF::R_390_PC16DBL; + case SystemZ::FK_390_PC24DBL: return ELF::R_390_PC24DBL; case SystemZ::FK_390_PC32DBL: return ELF::R_390_PC32DBL; } llvm_unreachable("Unsupported PC-relative address"); @@ -100,7 +102,9 @@ static unsigned getTLSGDReloc(unsigned Kind) { // Return the PLT relocation counterpart of MCFixupKind Kind. static unsigned getPLTReloc(unsigned Kind) { switch (Kind) { + case SystemZ::FK_390_PC12DBL: return ELF::R_390_PLT12DBL; case SystemZ::FK_390_PC16DBL: return ELF::R_390_PLT16DBL; + case SystemZ::FK_390_PC24DBL: return ELF::R_390_PLT24DBL; case SystemZ::FK_390_PC32DBL: return ELF::R_390_PLT32DBL; } llvm_unreachable("Unsupported absolute address"); diff --git a/llvm/lib/Target/SystemZ/SystemZFeatures.td b/llvm/lib/Target/SystemZ/SystemZFeatures.td index 0fb3c55..716e5ad 100644 --- a/llvm/lib/Target/SystemZ/SystemZFeatures.td +++ b/llvm/lib/Target/SystemZ/SystemZFeatures.td @@ -84,6 +84,11 @@ def Arch9NewFeatures : SystemZFeatureList<[ // //===----------------------------------------------------------------------===// +def FeatureExecutionHint : SystemZFeature< + "execution-hint", "ExecutionHint", + "Assume that the execution-hint facility is installed" +>; + def FeatureLoadAndTrap : SystemZFeature< "load-and-trap", "LoadAndTrap", "Assume that the load-and-trap facility is installed" @@ -105,6 +110,7 @@ def FeatureTransactionalExecution : SystemZFeature< >; def Arch10NewFeatures : SystemZFeatureList<[ + FeatureExecutionHint, FeatureLoadAndTrap, FeatureMiscellaneousExtensions, FeatureProcessorAssist, diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index a5c1c26..ad7c08b 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -177,6 +177,35 @@ class InstI op, dag outs, dag ins, string asmstr, list pattern> let Inst{7-0} = I1; } +class InstIE op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<4, outs, ins, asmstr, pattern> { + field bits<32> Inst; + field bits<32> SoftFail = 0; + + bits<4> I1; + bits<4> I2; + + let Inst{31-16} = op; + let Inst{15-8} = 0; + let Inst{7-4} = I1; + let Inst{3-0} = I2; +} + +class InstMII op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<4> M1; + bits<12> RI2; + bits<24> RI3; + + let Inst{47-40} = op; + let Inst{39-36} = M1; + let Inst{35-24} = RI2; + let Inst{23-0} = RI3; +} + class InstRIa op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; @@ -759,6 +788,22 @@ class InstSIY op, dag outs, dag ins, string asmstr, list pattern> let Has20BitOffset = 1; } +class InstSMI op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<4> M1; + bits<16> RI2; + bits<16> BD3; + + let Inst{47-40} = op; + let Inst{39-36} = M1; + let Inst{35-32} = 0; + let Inst{31-16} = BD3; + let Inst{15-0} = RI2; +} + class InstSSa op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; @@ -1605,6 +1650,9 @@ class ICV // One 4-bit immediate operand and one address operand. The immediate // operand is 1 for a load prefetch and 2 for a store prefetch. // +// BranchPreload: +// One 4-bit immediate operand and two address operands. +// // The format determines which input operands are tied to output operands, // and also determines the shape of any address operand. // @@ -2504,6 +2552,13 @@ class SideEffectBinaryRILPC opcode, let AddedComplexity = 7; } +class SideEffectBinaryIE opcode, + Immediate imm1, Immediate imm2> + : InstIE { + let hasSideEffects = 1; +} + class SideEffectBinarySIL opcode, SDPatternOperator operator, Immediate imm> : InstSIL opcode, let AddedComplexity = 7; } +class BranchPreloadSMI opcode> + : InstSMI; + +class BranchPreloadMII opcode> + : InstMII; + // A floating-point load-and test operation. Create both a normal unary // operation and one that acts as a comparison against zero. // Note that the comparison against zero operation is not available if we diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index c180d40..d97a92d 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1382,12 +1382,21 @@ def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; //===----------------------------------------------------------------------===// -// Prefetch +// Prefetch and execution hint //===----------------------------------------------------------------------===// def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; +let Predicates = [FeatureExecutionHint] in { + // Branch Prediction Preload + def BPP : BranchPreloadSMI<"bpp", 0xC7>; + def BPRP : BranchPreloadMII<"bprp", 0xC5>; + + // Next Instruction Access Intent + def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; +} + //===----------------------------------------------------------------------===// // Atomic operations //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td index 3b74749..7bb4fe5 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperands.td +++ b/llvm/lib/Target/SystemZ/SystemZOperands.td @@ -460,7 +460,9 @@ def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; //===----------------------------------------------------------------------===// // PC-relative asm operands. +def PCRel12 : PCRelAsmOperand<"12">; def PCRel16 : PCRelAsmOperand<"16">; +def PCRel24 : PCRelAsmOperand<"24">; def PCRel32 : PCRelAsmOperand<"32">; def PCRelTLS16 : PCRelTLSAsmOperand<"16">; def PCRelTLS32 : PCRelTLSAsmOperand<"32">; @@ -476,6 +478,20 @@ def brtarget32 : PCRelOperand { let DecoderMethod = "decodePC32DBLBranchOperand"; } +// Variants of brtarget for use with branch prediction preload. +def brtarget12bpp : PCRelOperand { + let EncoderMethod = "getPC12DBLBPPEncoding"; + let DecoderMethod = "decodePC12DBLBranchOperand"; +} +def brtarget16bpp : PCRelOperand { + let EncoderMethod = "getPC16DBLBPPEncoding"; + let DecoderMethod = "decodePC16DBLBranchOperand"; +} +def brtarget24bpp : PCRelOperand { + let EncoderMethod = "getPC24DBLBPPEncoding"; + let DecoderMethod = "decodePC24DBLBranchOperand"; +} + // Variants of brtarget16/32 with an optional additional TLS symbol. // These are used to annotate calls to __tls_get_offset. def tlssym : Operand { } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index f712d2b..ae6885f 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -517,10 +517,13 @@ def : InstRW<[FXb], (instregex "TMLH(64)?$")>; def : InstRW<[FXb], (instregex "TMLL(64)?$")>; //===----------------------------------------------------------------------===// -// Prefetch +// Prefetch and execution hint //===----------------------------------------------------------------------===// def : InstRW<[LSU], (instregex "PFD(RL)?$")>; +def : InstRW<[FXb, Lat2], (instregex "BPP$")>; +def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>; +def : InstRW<[FXb], (instregex "NIAI$")>; //===----------------------------------------------------------------------===// // Atomic operations diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index 49353eb..38d4402 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -487,10 +487,12 @@ def : InstRW<[FXU], (instregex "TMLH(64)?$")>; def : InstRW<[FXU], (instregex "TMLL(64)?$")>; //===----------------------------------------------------------------------===// -// Prefetch +// Prefetch and execution hint //===----------------------------------------------------------------------===// def : InstRW<[LSU], (instregex "PFD(RL)?$")>; +def : InstRW<[LSU], (instregex "BP(R)?P$")>; +def : InstRW<[FXU], (instregex "NIAI$")>; //===----------------------------------------------------------------------===// // Atomic operations diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index bf7277a..ce07ea3 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -39,8 +39,9 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), - HasLoadAndTrap(false), HasTransactionalExecution(false), - HasProcessorAssist(false), HasVector(false), HasLoadStoreOnCond2(false), + HasExecutionHint(false), HasLoadAndTrap(false), + HasTransactionalExecution(false), HasProcessorAssist(false), + HasVector(false), HasLoadStoreOnCond2(false), HasLoadAndZeroRightmostByte(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(), FrameLowering() {} diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h index 8475e2e..cdb6132 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -42,6 +42,7 @@ protected: bool HasFastSerialization; bool HasInterlockedAccess1; bool HasMiscellaneousExtensions; + bool HasExecutionHint; bool HasLoadAndTrap; bool HasTransactionalExecution; bool HasProcessorAssist; @@ -114,6 +115,9 @@ public: return HasMiscellaneousExtensions; } + // Return true if the target has the execution-hint facility. + bool hasExecutionHint() const { return HasExecutionHint; } + // Return true if the target has the load-and-trap facility. bool hasLoadAndTrap() const { return HasLoadAndTrap; } diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt index 8c6149e..7106053 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt @@ -1883,3 +1883,67 @@ # CHECK: brcth %r15, 0x100000a9c 0xcc 0xf6 0x7f 0xff 0xff 0xff +# 0x00000aa4: +# CHECK: bpp 0, 0xaa4, 0 +0xc7 0x00 0x00 0x00 0x00 0x00 + +# 0x00000aaa: +# CHECK: bpp 14, 0xaaa, 4095(%r3) +0xc7 0xe0 0x3f 0xff 0x00 0x00 + +# 0x00000ab0: +# CHECK: bpp 15, 0xab2, 0 +0xc7 0xf0 0x00 0x00 0x00 0x01 + +# 0x00000ab6: +# CHECK: bpp 0, 0xab4, 256(%r8) +0xc7 0x00 0x81 0x00 0xff 0xff + +# 0x00000abc: +# CHECK: bpp 14, 0xffffffffffff0abc, 0 +0xc7 0xe0 0x00 0x00 0x80 0x00 + +# 0x00000ac2: +# CHECK: bpp 15, 0x10ac0, 4095(%r7) +0xc7 0xf0 0x7f 0xff 0x7f 0xff + +# 0x00000ac8: +# CHECK: bprp 0, 0xac8, 0xac8 +0xc5 0x00 0x00 0x00 0x00 0x00 + +# 0x00000ace: +# CHECK: bprp 14, 0xace, 0xad0 +0xc5 0xe0 0x00 0x00 0x00 0x01 + +# 0x00000ad4: +# CHECK: bprp 15, 0xad4, 0xad2 +0xc5 0xf0 0x00 0xff 0xff 0xff + +# 0x00000ada: +# CHECK: bprp 0, 0xada, 0xffffffffff000ada +0xc5 0x00 0x00 0x80 0x00 0x00 + +# 0x00000ae0: +# CHECK: bprp 14, 0xae0, 0x1000ade +0xc5 0xe0 0x00 0x7f 0xff 0xff + +# 0x00000ae6: +# CHECK: bprp 14, 0xae8, 0xae6 +0xc5 0xe0 0x01 0x00 0x00 0x00 + +# 0x00000aec: +# CHECK: bprp 15, 0xaea, 0xaec +0xc5 0xff 0xff 0x00 0x00 0x00 + +# 0x00000af2: +# CHECK: bprp 0, 0xfffffffffffffaf2, 0xaf2 +0xc5 0x08 0x00 0x00 0x00 0x00 + +# 0x00000af8: +# CHECK: bprp 14, 0x1af6, 0xaf8 +0xc5 0xe7 0xff 0x00 0x00 0x00 + +# 0x00000afe: +# CHECK: bprp 15, 0xcfe, 0x2afe +0xc5 0xf1 0x00 0x00 0x10 0x00 + diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt index b19281a..c6295ac 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt @@ -8008,6 +8008,18 @@ # CHECK: ny %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x54 +# CHECK: niai 0, 0 +0xb2 0xfa 0x00 0x00 + +# CHECK: niai 15, 0 +0xb2 0xfa 0x00 0xf0 + +# CHECK: niai 0, 15 +0xb2 0xfa 0x00 0x0f + +# CHECK: niai 15, 15 +0xb2 0xfa 0x00 0xff + # CHECK: ntstg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x25 diff --git a/llvm/test/MC/SystemZ/fixups-zEC12.s b/llvm/test/MC/SystemZ/fixups-zEC12.s new file mode 100644 index 0000000..a2a64a8 --- /dev/null +++ b/llvm/test/MC/SystemZ/fixups-zEC12.s @@ -0,0 +1,34 @@ + +# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=zEC12 --show-encoding %s | FileCheck %s + +# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=zEC12 -filetype=obj %s | \ +# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL + +# CHECK: bpp 12, branch, 0 # encoding: [0xc7,0xc0,0x00,0x00,A,A] +# CHECK: # fixup A - offset: 4, value: branch+4, kind: FK_390_PC16DBL +# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_PC16DBL branch 0x4 + .align 16 + bpp 12, branch, 0 + +# CHECK: bpp 12, branch@PLT, 0 # encoding: [0xc7,0xc0,0x00,0x00,A,A] +# CHECK: # fixup A - offset: 4, value: branch@PLT+4, kind: FK_390_PC16DBL +# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_PLT16DBL branch 0x4 + .align 16 + bpp 12, branch@plt, 0 + +# CHECK: bprp 12, branch, target # encoding: [0xc5,0b1100AAAA,A,B,B,B] +# CHECK-NEXT: # fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL +# CHECK-NEXT: # fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL +# CHECK-REL: 0x{{[0-9A-F]*1}} R_390_PC12DBL branch 0x1 +# CHECK-REL: 0x{{[0-9A-F]*3}} R_390_PC24DBL target 0x3 + .align 16 + bprp 12, branch, target + +# CHECK: bprp 12, branch@PLT, target@PLT # encoding: [0xc5,0b1100AAAA,A,B,B,B] +# CHECK-NEXT: # fixup A - offset: 1, value: branch@PLT+1, kind: FK_390_PC12DBL +# CHECK-NEXT: # fixup B - offset: 3, value: target@PLT+3, kind: FK_390_PC24DBL +# CHECK-REL: 0x{{[0-9A-F]*1}} R_390_PLT12DBL branch 0x1 +# CHECK-REL: 0x{{[0-9A-F]*3}} R_390_PLT24DBL target 0x3 + .align 16 + bprp 12, branch@plt, target@plt + diff --git a/llvm/test/MC/SystemZ/insn-bad-z196.s b/llvm/test/MC/SystemZ/insn-bad-z196.s index f2771d2..31d0ec5 100644 --- a/llvm/test/MC/SystemZ/insn-bad-z196.s +++ b/llvm/test/MC/SystemZ/insn-bad-z196.s @@ -34,6 +34,16 @@ aih %r0, (-1 << 31) - 1 aih %r0, (1 << 31) +#CHECK: error: instruction requires: execution-hint +#CHECK: bpp 0, 0, 0 + + bpp 0, 0, 0 + +#CHECK: error: instruction requires: execution-hint +#CHECK: bprp 0, 0, 0 + + bprp 0, 0, 0 + #CHECK: error: offset out of range #CHECK: brcth %r0, -0x1000000002 #CHECK: error: offset out of range @@ -747,6 +757,11 @@ locr %r0,%r0,-1 locr %r0,%r0,16 +#CHECK: error: instruction requires: execution-hint +#CHECK: niai 0, 0 + + niai 0, 0 + #CHECK: error: instruction requires: transactional-execution #CHECK: ntstg %r0, 524287(%r1,%r15) diff --git a/llvm/test/MC/SystemZ/insn-bad-zEC12.s b/llvm/test/MC/SystemZ/insn-bad-zEC12.s index a88fe7e..53dbd63 100644 --- a/llvm/test/MC/SystemZ/insn-bad-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-bad-zEC12.s @@ -5,6 +5,64 @@ # RUN: FileCheck < %t %s #CHECK: error: invalid operand +#CHECK: bpp -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: bpp 16, 0, 0 +#CHECK: error: offset out of range +#CHECK: bpp 0, -0x10002, 0 +#CHECK: error: offset out of range +#CHECK: bpp 0, -1, 0 +#CHECK: error: offset out of range +#CHECK: bpp 0, 1, 0 +#CHECK: error: offset out of range +#CHECK: bpp 0, 0x10000, 0 +#CHECK: error: invalid operand +#CHECK: bpp 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: bpp 0, 0, 4096 + + bpp -1, 0, 0 + bpp 16, 0, 0 + bpp 0, -0x10002, 0 + bpp 0, -1, 0 + bpp 0, 1, 0 + bpp 0, 0x10000, 0 + bpp 0, 0, -1 + bpp 0, 0, 4096 + +#CHECK: error: invalid operand +#CHECK: bprp -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: bprp 16, 0, 0 +#CHECK: error: offset out of range +#CHECK: bprp 0, -0x1002, 0 +#CHECK: error: offset out of range +#CHECK: bprp 0, -1, 0 +#CHECK: error: offset out of range +#CHECK: bprp 0, 1, 0 +#CHECK: error: offset out of range +#CHECK: bprp 0, 0x1000, 0 +#CHECK: error: offset out of range +#CHECK: bprp 0, 0, -0x1000002 +#CHECK: error: offset out of range +#CHECK: bprp 0, 0, -1 +#CHECK: error: offset out of range +#CHECK: bprp 0, 0, 1 +#CHECK: error: offset out of range +#CHECK: bprp 0, 0, 0x1000000 + + bprp -1, 0, 0 + bprp 16, 0, 0 + bprp 0, -0x1002, 0 + bprp 0, -1, 0 + bprp 0, 1, 0 + bprp 0, 0x1000, 0 + bprp 0, 0, -0x1000002 + bprp 0, 0, -1 + bprp 0, 0, 1 + bprp 0, 0, 0x1000000 + +#CHECK: error: invalid operand #CHECK: clt %r0, -1, 0 #CHECK: error: invalid operand #CHECK: clt %r0, 16, 0 @@ -100,6 +158,20 @@ lcbb %r0, 0, 0 #CHECK: error: invalid operand +#CHECK: niai -1, 0 +#CHECK: error: invalid operand +#CHECK: niai 16, 0 +#CHECK: error: invalid operand +#CHECK: niai 0, -1 +#CHECK: error: invalid operand +#CHECK: niai 0, 16 + + niai -1, 0 + niai 16, 0 + niai 0, -1 + niai 0, 16 + +#CHECK: error: invalid operand #CHECK: ntstg %r0, -524289 #CHECK: error: invalid operand #CHECK: ntstg %r0, 524288 diff --git a/llvm/test/MC/SystemZ/insn-good-zEC12.s b/llvm/test/MC/SystemZ/insn-good-zEC12.s index cb604f9..bdaeef9 100644 --- a/llvm/test/MC/SystemZ/insn-good-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-good-zEC12.s @@ -2,6 +2,118 @@ # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch10 -show-encoding %s | FileCheck %s +#CHECK: bpp 0, .[[LAB:L.*]]-65536, 0 # encoding: [0xc7,0x00,0x00,0x00,A,A] +#CHECK: fixup A - offset: 4, value: (.[[LAB]]-65536)+4, kind: FK_390_PC16DBL + bpp 0, -0x10000, 0 +#CHECK: bpp 0, .[[LAB:L.*]]-2, 0 # encoding: [0xc7,0x00,0x00,0x00,A,A] +#CHECK: fixup A - offset: 4, value: (.[[LAB]]-2)+4, kind: FK_390_PC16DBL + bpp 0, -2, 0 +#CHECK: bpp 0, .[[LAB:L.*]], 0 # encoding: [0xc7,0x00,0x00,0x00,A,A] +#CHECK: fixup A - offset: 4, value: .[[LAB]]+4, kind: FK_390_PC16DBL + bpp 0, 0, 0 +#CHECK: bpp 0, .[[LAB:L.*]]+65534, 0 # encoding: [0xc7,0x00,0x00,0x00,A,A] +#CHECK: fixup A - offset: 4, value: (.[[LAB]]+65534)+4, kind: FK_390_PC16DBL + bpp 0, 0xfffe, 0 + +#CHECK: bpp 0, foo, 4095(%r3) # encoding: [0xc7,0x00,0x3f,0xff,A,A] +#CHECK: fixup A - offset: 4, value: foo+4, kind: FK_390_PC16DBL +#CHECK: bpp 15, foo, 1(%r11) # encoding: [0xc7,0xf0,0xb0,0x01,A,A] +#CHECK: fixup A - offset: 4, value: foo+4, kind: FK_390_PC16DBL + + bpp 0, foo, 4095(%r3) + bpp 15, foo, 1(%r11) + +#CHECK: bpp 3, bar+100, 4095 # encoding: [0xc7,0x30,0x0f,0xff,A,A] +#CHECK: fixup A - offset: 4, value: (bar+100)+4, kind: FK_390_PC16DBL +#CHECK: bpp 4, bar+100, 1 # encoding: [0xc7,0x40,0x00,0x01,A,A] +#CHECK: fixup A - offset: 4, value: (bar+100)+4, kind: FK_390_PC16DBL + + bpp 3, bar+100, 4095 + bpp 4, bar+100, 1 + +#CHECK: bpp 7, frob@PLT, 0 # encoding: [0xc7,0x70,0x00,0x00,A,A] +#CHECK: fixup A - offset: 4, value: frob@PLT+4, kind: FK_390_PC16DBL +#CHECK: bpp 8, frob@PLT, 0 # encoding: [0xc7,0x80,0x00,0x00,A,A] +#CHECK: fixup A - offset: 4, value: frob@PLT+4, kind: FK_390_PC16DBL + + bpp 7, frob@PLT, 0 + bpp 8, frob@PLT, 0 + +#CHECK: bprp 0, .[[LABA:L.*]]-4096, .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: (.[[LABA]]-4096)+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL + bprp 0, -0x1000, 0 +#CHECK: bprp 0, .[[LABA:L.*]]-2, .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: (.[[LABA]]-2)+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL + bprp 0, -2, 0 +#CHECK: bprp 0, .[[LABA:L.*]], .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL + bprp 0, 0, 0 +#CHECK: bprp 0, .[[LABA:L.*]]+4094, .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: (.[[LABA]]+4094)+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL + bprp 0, 0xffe, 0 +#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]]-16777216 # encoding: [0xc5,0b1111AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: (.[[LABB]]-16777216)+3, kind: FK_390_PC24DBL + bprp 15, 0, -0x1000000 +#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]]-2 # encoding: [0xc5,0b1111AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: (.[[LABB]]-2)+3, kind: FK_390_PC24DBL + bprp 15, 0, -2 +#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]] # encoding: [0xc5,0b1111AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL + bprp 15, 0, 0 +#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]]+16777214 # encoding: [0xc5,0b1111AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: (.[[LABB]]+16777214)+3, kind: FK_390_PC24DBL + bprp 15, 0, 0xfffffe + +#CHECK: bprp 1, branch, target # encoding: [0xc5,0b0001AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL +#CHECK: bprp 2, branch, target # encoding: [0xc5,0b0010AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL +#CHECK: bprp 3, branch, target # encoding: [0xc5,0b0011AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL + + bprp 1, branch, target + bprp 2, branch, target + bprp 3, branch, target + +#CHECK: bprp 4, branch+100, target # encoding: [0xc5,0b0100AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: (branch+100)+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL +#CHECK: bprp 5, branch, target+100 # encoding: [0xc5,0b0101AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: (target+100)+3, kind: FK_390_PC24DBL +#CHECK: bprp 6, branch+100, target+100 # encoding: [0xc5,0b0110AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: (branch+100)+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: (target+100)+3, kind: FK_390_PC24DBL + + bprp 4, branch+100, target + bprp 5, branch, target+100 + bprp 6, branch+100, target+100 + +#CHECK: bprp 7, branch@PLT, target # encoding: [0xc5,0b0111AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch@PLT+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL +#CHECK: bprp 8, branch, target@PLT # encoding: [0xc5,0b1000AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target@PLT+3, kind: FK_390_PC24DBL +#CHECK: bprp 9, branch@PLT, target@PLT # encoding: [0xc5,0b1001AAAA,A,B,B,B] +#CHECK: fixup A - offset: 1, value: branch@PLT+1, kind: FK_390_PC12DBL +#CHECK: fixup B - offset: 3, value: target@PLT+3, kind: FK_390_PC24DBL + + bprp 7, branch@plt, target + bprp 8, branch, target@plt + bprp 9, branch@plt, target@plt + #CHECK: clt %r0, 12, -524288 # encoding: [0xeb,0x0c,0x00,0x00,0x80,0x23] #CHECK: clt %r0, 12, -1 # encoding: [0xeb,0x0c,0x0f,0xff,0xff,0x23] #CHECK: clt %r0, 12, 0 # encoding: [0xeb,0x0c,0x00,0x00,0x00,0x23] @@ -184,6 +296,16 @@ etnd %r15 etnd %r7 +#CHECK: niai 0, 0 # encoding: [0xb2,0xfa,0x00,0x00] +#CHECK: niai 15, 0 # encoding: [0xb2,0xfa,0x00,0xf0] +#CHECK: niai 0, 15 # encoding: [0xb2,0xfa,0x00,0x0f] +#CHECK: niai 15, 15 # encoding: [0xb2,0xfa,0x00,0xff] + + niai 0, 0 + niai 15, 0 + niai 0, 15 + niai 15, 15 + #CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25] #CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25] #CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25] -- 2.7.4