From 8335d6aa34b88ce31b62e1b578d54ab4aa364435 Mon Sep 17 00:00:00 2001 From: Jiong Wang Date: Tue, 8 Jul 2014 12:14:56 +0100 Subject: [PATCH] Fix PR 16722 by adding support for 8-byte vector constants. * config/tc-arm.c (literal_pool): New field "alignment". (find_or_make_literal_pool): Initialize "alignment" to 2. (s_ltorg): Align the pool using value of "alignment" (parse_big_immediate): New parameter "in_exp". Return parsed expression if "in_exp" is not null. (parse_address_main): Invoke "parse_big_immediate" for constant parameter. (add_to_lit_pool): Add one parameter 'nbytes'. Split 8 byte entry into two 4 byte entry. Add padding to align 8 byte entry to 8 byte boundary. (encode_arm_cp_address): Generate literal pool entry if possible. (move_or_literal_pool): Generate entry for vldr case. (enum lit_type): New enum type. (do_ldst): Use new enum type. (do_ldstv4): Likewise. (do_t_ldst): Likewise. (neon_write_immbits): Support Thumb-2 mode. * gas/arm/ldconst.s: Add test cases for symbol literal. * gas/arm/ldconst.d: Likewise. * gas/arm/vldconst.s: Add test cases for vldr. * gas/arm/thumb2_vpool.s: Likewise. * gas/arm/vldconst.d: New pattern for little-endian. * gas/arm/thumb2_vpool.d: Likewise. * gas/arm/vldconst_be.d: New pattern for big-endian. * gas/arm/thumb2_vpool_be.d: Likewise. --- gas/ChangeLog | 20 + gas/config/tc-arm.c | 807 ++++++++++++++++---------- gas/testsuite/ChangeLog | 21 + gas/testsuite/gas/arm/armv8-a+crypto.d | 1 + gas/testsuite/gas/arm/armv8-a+fp.d | 1 + gas/testsuite/gas/arm/armv8-a+simd.d | 1 + gas/testsuite/gas/arm/armv8-a-barrier-thumb.d | 1 + gas/testsuite/gas/arm/bl-local-2.d | 1 + gas/testsuite/gas/arm/ldconst.d | 15 + gas/testsuite/gas/arm/ldconst.s | 11 + gas/testsuite/gas/arm/ldgesb-bad.d | 1 + gas/testsuite/gas/arm/ldgesh-bad.d | 1 + gas/testsuite/gas/arm/thumb2_pool.d | 15 + gas/testsuite/gas/arm/thumb2_pool.s | 11 + gas/testsuite/gas/arm/thumb2_vpool.d | 169 ++++++ gas/testsuite/gas/arm/thumb2_vpool.s | 95 +++ gas/testsuite/gas/arm/thumb2_vpool_be.d | 176 ++++++ gas/testsuite/gas/arm/vldconst.d | 280 +++++++++ gas/testsuite/gas/arm/vldconst.s | 146 +++++ gas/testsuite/gas/arm/vldconst_be.d | 285 +++++++++ 20 files changed, 1739 insertions(+), 319 deletions(-) create mode 100644 gas/testsuite/gas/arm/thumb2_vpool.d create mode 100644 gas/testsuite/gas/arm/thumb2_vpool.s create mode 100644 gas/testsuite/gas/arm/thumb2_vpool_be.d create mode 100644 gas/testsuite/gas/arm/vldconst.d create mode 100644 gas/testsuite/gas/arm/vldconst.s create mode 100644 gas/testsuite/gas/arm/vldconst_be.d diff --git a/gas/ChangeLog b/gas/ChangeLog index ec38771..9c183e4 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,23 @@ +2014-07-08 Jiong Wang + + * config/tc-arm.c (literal_pool): New field "alignment". + (find_or_make_literal_pool): Initialize "alignment" to 2. + (s_ltorg): Align the pool using value of "alignment" + (parse_big_immediate): New parameter "in_exp". Return + parsed expression if "in_exp" is not null. + (parse_address_main): Invoke "parse_big_immediate" for + constant parameter. + (add_to_lit_pool): Add one parameter 'nbytes'. + Split 8 byte entry into two 4 byte entry. + Add padding to align 8 byte entry to 8 byte boundary. + (encode_arm_cp_address): Generate literal pool entry if possible. + (move_or_literal_pool): Generate entry for vldr case. + (enum lit_type): New enum type. + (do_ldst): Use new enum type. + (do_ldstv4): Likewise. + (do_t_ldst): Likewise. + (neon_write_immbits): Support Thumb-2 mode. + 2014-07-07 Barney Stratford * config/tc-avr.c (avr_operand): Permit referring to r26-r31 by diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index ce0532b..2f13238 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -630,6 +630,7 @@ struct asm_opcode #define LITERAL_MASK 0xf000f000 #define OPCODE_MASK 0xfe1fffff #define V4_STR_BIT 0x00000020 +#define VLDR_VMOV_SAME 0x0040f000 #define T2_SUBS_PC_LR 0xf3de8f00 @@ -792,6 +793,7 @@ typedef struct literal_pool struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; #endif struct literal_pool * next; + unsigned int alignment; } literal_pool; /* Pointer to a linked list of literal pools. */ @@ -3159,6 +3161,7 @@ find_or_make_literal_pool (void) pool->sub_section = now_subseg; pool->next = list_of_pools; pool->symbol = NULL; + pool->alignment = 2; /* Add it to the list. */ list_of_pools = pool; @@ -3180,33 +3183,74 @@ find_or_make_literal_pool (void) structure to the relevant literal pool. */ static int -add_to_lit_pool (void) +add_to_lit_pool (unsigned int nbytes) { +#define PADDING_SLOT 0x1 +#define LIT_ENTRY_SIZE_MASK 0xFF literal_pool * pool; - unsigned int entry; + unsigned int entry, pool_size = 0; + bfd_boolean padding_slot_p = FALSE; + unsigned imm1; + unsigned imm2 = 0; + + if (nbytes == 8) + { + imm1 = inst.operands[1].imm; + imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg + : inst.reloc.exp.X_unsigned ? 0 + : ((int64_t)(imm1)) >> 32); + if (target_big_endian) + { + imm1 = imm2; + imm2 = inst.operands[1].imm; + } + } pool = find_or_make_literal_pool (); /* Check if this literal value is already in the pool. */ for (entry = 0; entry < pool->next_free_entry; entry ++) { - if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) - && (inst.reloc.exp.X_op == O_constant) - && (pool->literals[entry].X_add_number - == inst.reloc.exp.X_add_number) - && (pool->literals[entry].X_unsigned - == inst.reloc.exp.X_unsigned)) + if (nbytes == 4) + { + if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) + && (inst.reloc.exp.X_op == O_constant) + && (pool->literals[entry].X_add_number + == inst.reloc.exp.X_add_number) + && (pool->literals[entry].X_md == nbytes) + && (pool->literals[entry].X_unsigned + == inst.reloc.exp.X_unsigned)) + break; + + if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) + && (inst.reloc.exp.X_op == O_symbol) + && (pool->literals[entry].X_add_number + == inst.reloc.exp.X_add_number) + && (pool->literals[entry].X_add_symbol + == inst.reloc.exp.X_add_symbol) + && (pool->literals[entry].X_op_symbol + == inst.reloc.exp.X_op_symbol) + && (pool->literals[entry].X_md == nbytes)) + break; + } + else if ((nbytes == 8) + && !(pool_size & 0x7) + && ((entry + 1) != pool->next_free_entry) + && (pool->literals[entry].X_op == O_constant) + && (pool->literals[entry].X_add_number == imm1) + && (pool->literals[entry].X_unsigned + == inst.reloc.exp.X_unsigned) + && (pool->literals[entry + 1].X_op == O_constant) + && (pool->literals[entry + 1].X_add_number == imm2) + && (pool->literals[entry + 1].X_unsigned + == inst.reloc.exp.X_unsigned)) break; - if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) - && (inst.reloc.exp.X_op == O_symbol) - && (pool->literals[entry].X_add_number - == inst.reloc.exp.X_add_number) - && (pool->literals[entry].X_add_symbol - == inst.reloc.exp.X_add_symbol) - && (pool->literals[entry].X_op_symbol - == inst.reloc.exp.X_op_symbol)) + padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT); + if (padding_slot_p && (nbytes == 4)) break; + + pool_size += 4; } /* Do we need to create a new entry? */ @@ -3218,7 +3262,64 @@ add_to_lit_pool (void) return FAIL; } - pool->literals[entry] = inst.reloc.exp; + if (nbytes == 8) + { + /* For 8-byte entries, we align to an 8-byte boundary, + and split it into two 4-byte entries, because on 32-bit + host, 8-byte constants are treated as big num, thus + saved in "generic_bignum" which will be overwritten + by later assignments. + + We also need to make sure there is enough space for + the split. + + We also check to make sure the literal operand is a + constant number. */ + if (!(inst.reloc.exp.X_op == O_constant) + || (inst.reloc.exp.X_op == O_big)) + { + inst.error = _("invalid type for literal pool"); + return FAIL; + } + else if (pool_size & 0x7) + { + if ((entry + 2) >= MAX_LITERAL_POOL_SIZE) + { + inst.error = _("literal pool overflow"); + return FAIL; + } + + pool->literals[entry] = inst.reloc.exp; + pool->literals[entry].X_add_number = 0; + pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4; + pool->next_free_entry += 1; + pool_size += 4; + } + else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE) + { + inst.error = _("literal pool overflow"); + return FAIL; + } + + pool->literals[entry] = inst.reloc.exp; + pool->literals[entry].X_op = O_constant; + pool->literals[entry].X_add_number = imm1; + pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; + pool->literals[entry++].X_md = 4; + pool->literals[entry] = inst.reloc.exp; + pool->literals[entry].X_op = O_constant; + pool->literals[entry].X_add_number = imm2; + pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned; + pool->literals[entry].X_md = 4; + pool->alignment = 3; + pool->next_free_entry += 1; + } + else + { + pool->literals[entry] = inst.reloc.exp; + pool->literals[entry].X_md = 4; + } + #ifdef OBJ_ELF /* PR ld/12974: Record the location of the first source line to reference this entry in the literal pool. If it turns out during linking that the @@ -3229,9 +3330,14 @@ add_to_lit_pool (void) #endif pool->next_free_entry += 1; } + else if (padding_slot_p) + { + pool->literals[entry] = inst.reloc.exp; + pool->literals[entry].X_md = nbytes; + } inst.reloc.exp.X_op = O_symbol; - inst.reloc.exp.X_add_number = ((int) entry) * 4; + inst.reloc.exp.X_add_number = pool_size; inst.reloc.exp.X_add_symbol = pool->symbol; return SUCCESS; @@ -3314,7 +3420,6 @@ symbol_locate (symbolS * symbolP, #endif /* DEBUG_SYMS */ } - static void s_ltorg (int ignored ATTRIBUTE_UNUSED) { @@ -3331,7 +3436,7 @@ s_ltorg (int ignored ATTRIBUTE_UNUSED) /* Align pool as you have word accesses. Only make a frag if we have to. */ if (!need_pass_2) - frag_align (2, 0, 0); + frag_align (pool->alignment, 0, 0); record_alignment (now_seg, 2); @@ -3358,7 +3463,8 @@ s_ltorg (int ignored ATTRIBUTE_UNUSED) dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); #endif /* First output the expression in the instruction to the pool. */ - emit_expr (&(pool->literals[entry]), 4); /* .word */ + emit_expr (&(pool->literals[entry]), + pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK); } /* Mark the pool as empty. */ @@ -4669,28 +4775,31 @@ parse_immediate (char **str, int *val, int min, int max, instructions. Puts the result directly in inst.operands[i]. */ static int -parse_big_immediate (char **str, int i) +parse_big_immediate (char **str, int i, expressionS *in_exp, + bfd_boolean allow_symbol_p) { expressionS exp; + expressionS *exp_p = in_exp ? in_exp : &exp; char *ptr = *str; - my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); + my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG); - if (exp.X_op == O_constant) + if (exp_p->X_op == O_constant) { - inst.operands[i].imm = exp.X_add_number & 0xffffffff; + inst.operands[i].imm = exp_p->X_add_number & 0xffffffff; /* If we're on a 64-bit host, then a 64-bit number can be returned using O_constant. We have to be careful not to break compilation for 32-bit X_add_number, though. */ - if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0) + if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0) { - /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ - inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; + /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */ + inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16) + & 0xffffffff); inst.operands[i].regisimm = 1; } } - else if (exp.X_op == O_big - && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) + else if (exp_p->X_op == O_big + && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32) { unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; @@ -4703,7 +4812,7 @@ parse_big_immediate (char **str, int i) PR 11972: Bignums can now be sign-extended to the size of a .octa so check that the out of range bits are all zero or all one. */ - if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) + if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64) { LITTLENUM_TYPE m = -1; @@ -4711,7 +4820,7 @@ parse_big_immediate (char **str, int i) && generic_bignum[parts * 2] != m) return FAIL; - for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) + for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++) if (generic_bignum[j] != generic_bignum[j-1]) return FAIL; } @@ -4726,7 +4835,7 @@ parse_big_immediate (char **str, int i) << (LITTLENUM_NUMBER_OF_BITS * j); inst.operands[i].regisimm = 1; } - else + else if (!(exp_p->X_op == O_symbol && allow_symbol_p)) return FAIL; *str = ptr; @@ -5319,10 +5428,12 @@ parse_address_main (char **str, int i, int group_relocations, inst.operands[i].reg = REG_PC; inst.operands[i].isreg = 1; inst.operands[i].preind = 1; - } - /* Otherwise a load-constant pseudo op, no special treatment needed here. */ - if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) + if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG)) + return PARSE_OPERAND_FAIL; + } + else if (parse_big_immediate (&p, i, &inst.reloc.exp, + /*allow_symbol_p=*/TRUE)) return PARSE_OPERAND_FAIL; *str = p; @@ -6152,7 +6263,8 @@ parse_neon_mov (char **str, int *which_operand) Case 10: VMOV.F32 , # Case 11: VMOV.F64
, # */ inst.operands[i].immisfloat = 1; - else if (parse_big_immediate (&ptr, i) == SUCCESS) + else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE) + == SUCCESS) /* Case 2: VMOV.
, # Case 3: VMOV.
, # */ ; @@ -6637,7 +6749,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) try_immbig: /* There's a possibility of getting a 64-bit immediate here, so we need special handling. */ - if (parse_big_immediate (&str, i) == FAIL) + if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE) + == FAIL) { inst.error = _("immediate value is out of range"); goto failure; @@ -7378,71 +7491,204 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t) } } -/* inst.operands[i] was set up by parse_address. Encode it into an - ARM-format instruction. Reject all forms which cannot be encoded - into a coprocessor load/store instruction. If wb_ok is false, - reject use of writeback; if unind_ok is false, reject use of - unindexed addressing. If reloc_override is not 0, use it instead - of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one - (in which case it is preserved). */ +/* Write immediate bits [7:0] to the following locations: + + |28/24|23 19|18 16|15 4|3 0| + | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| + + This function is used by VMOV/VMVN/VORR/VBIC. */ + +static void +neon_write_immbits (unsigned immbits) +{ + inst.instruction |= immbits & 0xf; + inst.instruction |= ((immbits >> 4) & 0x7) << 16; + inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24); +} + +/* Invert low-order SIZE bits of XHI:XLO. */ + +static void +neon_invert_size (unsigned *xlo, unsigned *xhi, int size) +{ + unsigned immlo = xlo ? *xlo : 0; + unsigned immhi = xhi ? *xhi : 0; + + switch (size) + { + case 8: + immlo = (~immlo) & 0xff; + break; + + case 16: + immlo = (~immlo) & 0xffff; + break; + + case 64: + immhi = (~immhi) & 0xffffffff; + /* fall through. */ + + case 32: + immlo = (~immlo) & 0xffffffff; + break; + + default: + abort (); + } + + if (xlo) + *xlo = immlo; + + if (xhi) + *xhi = immhi; +} + +/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits + A, B, C, D. */ static int -encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) +neon_bits_same_in_bytes (unsigned imm) { - inst.instruction |= inst.operands[i].reg << 16; + return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) + && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) + && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) + && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); +} - gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); +/* For immediate of above form, return 0bABCD. */ - if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ +static unsigned +neon_squash_bits (unsigned imm) +{ + return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) + | ((imm & 0x01000000) >> 21); +} + +/* Compress quarter-float representation to 0b...000 abcdefgh. */ + +static unsigned +neon_qfloat_bits (unsigned imm) +{ + return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); +} + +/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into + the instruction. *OP is passed as the initial value of the op field, and + may be set to a different value depending on the constant (i.e. + "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not + MVN). If the immediate looks like a repeated pattern then also + try smaller element sizes. */ + +static int +neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, + unsigned *immbits, int *op, int size, + enum neon_el_type type) +{ + /* Only permit float immediates (including 0.0/-0.0) if the operand type is + float. */ + if (type == NT_float && !float_p) + return FAIL; + + if (type == NT_float && is_quarter_float (immlo) && immhi == 0) { - gas_assert (!inst.operands[i].writeback); - if (!unind_ok) + if (size != 32 || *op == 1) + return FAIL; + *immbits = neon_qfloat_bits (immlo); + return 0xf; + } + + if (size == 64) + { + if (neon_bits_same_in_bytes (immhi) + && neon_bits_same_in_bytes (immlo)) { - inst.error = _("instruction does not support unindexed addressing"); - return FAIL; + if (*op == 1) + return FAIL; + *immbits = (neon_squash_bits (immhi) << 4) + | neon_squash_bits (immlo); + *op = 1; + return 0xe; } - inst.instruction |= inst.operands[i].imm; - inst.instruction |= INDEX_UP; - return SUCCESS; - } - if (inst.operands[i].preind) - inst.instruction |= PRE_INDEX; + if (immhi != immlo) + return FAIL; + } - if (inst.operands[i].writeback) + if (size >= 32) { - if (inst.operands[i].reg == REG_PC) + if (immlo == (immlo & 0x000000ff)) { - inst.error = _("pc may not be used with write-back"); - return FAIL; + *immbits = immlo; + return 0x0; } - if (!wb_ok) + else if (immlo == (immlo & 0x0000ff00)) { - inst.error = _("instruction does not support writeback"); - return FAIL; + *immbits = immlo >> 8; + return 0x2; } - inst.instruction |= WRITE_BACK; + else if (immlo == (immlo & 0x00ff0000)) + { + *immbits = immlo >> 16; + return 0x4; + } + else if (immlo == (immlo & 0xff000000)) + { + *immbits = immlo >> 24; + return 0x6; + } + else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) + { + *immbits = (immlo >> 8) & 0xff; + return 0xc; + } + else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) + { + *immbits = (immlo >> 16) & 0xff; + return 0xd; + } + + if ((immlo & 0xffff) != (immlo >> 16)) + return FAIL; + immlo &= 0xffff; } - if (reloc_override) - inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; - else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC - || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) - && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) + if (size >= 16) { - if (thumb_mode) - inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; - else - inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; + if (immlo == (immlo & 0x000000ff)) + { + *immbits = immlo; + return 0x8; + } + else if (immlo == (immlo & 0x0000ff00)) + { + *immbits = immlo >> 8; + return 0xa; + } + + if ((immlo & 0xff) != (immlo >> 8)) + return FAIL; + immlo &= 0xff; } - /* Prefer + for zero encoded value. */ - if (!inst.operands[i].negative) - inst.instruction |= INDEX_UP; + if (immlo == (immlo & 0x000000ff)) + { + /* Don't allow MVN with 8-bit immediate. */ + if (*op == 1) + return FAIL; + *immbits = immlo; + return 0xe; + } - return SUCCESS; + return FAIL; } +enum lit_type +{ + CONST_THUMB, + CONST_ARM, + CONST_VEC +}; + /* inst.reloc.exp describes an "=expr" load pseudo-operation. Determine whether it can be performed with a move instruction; if it can, convert inst.instruction to that move instruction and @@ -7453,9 +7699,12 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) inst.operands[i] describes the destination register. */ static bfd_boolean -move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) +move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) { unsigned long tbit; + bfd_boolean thumb_p = (t == CONST_THUMB); + bfd_boolean arm_p = (t == CONST_ARM); + bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle; if (thumb_p) tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; @@ -7467,62 +7716,173 @@ move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) inst.error = _("invalid pseudo operation"); return TRUE; } - if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) + if (inst.reloc.exp.X_op != O_constant + && inst.reloc.exp.X_op != O_symbol + && inst.reloc.exp.X_op != O_big) { inst.error = _("constant expression expected"); return TRUE; } - if (inst.reloc.exp.X_op == O_constant) + if ((inst.reloc.exp.X_op == O_constant + || inst.reloc.exp.X_op == O_big) + && !inst.operands[i].issingle) + { + if (thumb_p && inst.reloc.exp.X_op == O_constant) + { + if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) + { + /* This can be done with a mov(1) instruction. */ + inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); + inst.instruction |= inst.reloc.exp.X_add_number; + return TRUE; + } + } + else if (arm_p && inst.reloc.exp.X_op == O_constant) + { + int value = encode_arm_immediate (inst.reloc.exp.X_add_number); + if (value != FAIL) + { + /* This can be done with a mov instruction. */ + inst.instruction &= LITERAL_MASK; + inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); + inst.instruction |= value & 0xfff; + return TRUE; + } + + value = encode_arm_immediate (~inst.reloc.exp.X_add_number); + if (value != FAIL) + { + /* This can be done with a mvn instruction. */ + inst.instruction &= LITERAL_MASK; + inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); + inst.instruction |= value & 0xfff; + return TRUE; + } + } + else if (vec64_p) + { + int op = 0; + unsigned immbits = 0; + unsigned immlo = inst.operands[1].imm; + unsigned immhi = inst.operands[1].regisimm + ? inst.operands[1].reg + : inst.reloc.exp.X_unsigned + ? 0 + : ((int64_t)((int) immlo)) >> 32; + int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, + &op, 64, NT_invtype); + + if (cmode == FAIL) + { + neon_invert_size (&immlo, &immhi, 64); + op = !op; + cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits, + &op, 64, NT_invtype); + } + if (cmode != FAIL) + { + inst.instruction = (inst.instruction & VLDR_VMOV_SAME) + | (1 << 23) + | (cmode << 8) + | (op << 5) + | (1 << 4); + /* Fill other bits in vmov encoding for both thumb and arm. */ + if (thumb_mode) + inst.instruction |= (0x7 << 29) | (0xF << 24); + else + inst.instruction |= (0xF << 28) | (0x1 << 25); + neon_write_immbits (immbits); + return TRUE; + } + } + } + + if (add_to_lit_pool ((!inst.operands[i].isvec + || inst.operands[i].issingle) ? 4 : 8) == FAIL) + return TRUE; + + inst.operands[1].reg = REG_PC; + inst.operands[1].isreg = 1; + inst.operands[1].preind = 1; + inst.reloc.pc_rel = 1; + inst.reloc.type = (thumb_p + ? BFD_RELOC_ARM_THUMB_OFFSET + : (mode_3 + ? BFD_RELOC_ARM_HWLITERAL + : BFD_RELOC_ARM_LITERAL)); + return FALSE; +} + +/* inst.operands[i] was set up by parse_address. Encode it into an + ARM-format instruction. Reject all forms which cannot be encoded + into a coprocessor load/store instruction. If wb_ok is false, + reject use of writeback; if unind_ok is false, reject use of + unindexed addressing. If reloc_override is not 0, use it instead + of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one + (in which case it is preserved). */ + +static int +encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) +{ + if (!inst.operands[i].isreg) + { + gas_assert (inst.operands[0].isvec); + if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE)) + return SUCCESS; + } + + inst.instruction |= inst.operands[i].reg << 16; + + gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); + + if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ + { + gas_assert (!inst.operands[i].writeback); + if (!unind_ok) + { + inst.error = _("instruction does not support unindexed addressing"); + return FAIL; + } + inst.instruction |= inst.operands[i].imm; + inst.instruction |= INDEX_UP; + return SUCCESS; + } + + if (inst.operands[i].preind) + inst.instruction |= PRE_INDEX; + + if (inst.operands[i].writeback) { - if (thumb_p) + if (inst.operands[i].reg == REG_PC) { - if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) - { - /* This can be done with a mov(1) instruction. */ - inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); - inst.instruction |= inst.reloc.exp.X_add_number; - return TRUE; - } + inst.error = _("pc may not be used with write-back"); + return FAIL; } - else + if (!wb_ok) { - int value = encode_arm_immediate (inst.reloc.exp.X_add_number); - if (value != FAIL) - { - /* This can be done with a mov instruction. */ - inst.instruction &= LITERAL_MASK; - inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); - inst.instruction |= value & 0xfff; - return TRUE; - } - - value = encode_arm_immediate (~inst.reloc.exp.X_add_number); - if (value != FAIL) - { - /* This can be done with a mvn instruction. */ - inst.instruction &= LITERAL_MASK; - inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); - inst.instruction |= value & 0xfff; - return TRUE; - } + inst.error = _("instruction does not support writeback"); + return FAIL; } + inst.instruction |= WRITE_BACK; } - if (add_to_lit_pool () == FAIL) + if (reloc_override) + inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; + else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC + || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) + && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) { - inst.error = _("literal pool insertion failed"); - return TRUE; + if (thumb_mode) + inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; + else + inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; } - inst.operands[1].reg = REG_PC; - inst.operands[1].isreg = 1; - inst.operands[1].preind = 1; - inst.reloc.pc_rel = 1; - inst.reloc.type = (thumb_p - ? BFD_RELOC_ARM_THUMB_OFFSET - : (mode_3 - ? BFD_RELOC_ARM_HWLITERAL - : BFD_RELOC_ARM_LITERAL)); - return FALSE; + + /* Prefer + for zero encoded value. */ + if (!inst.operands[i].negative) + inst.instruction |= INDEX_UP; + + return SUCCESS; } /* Functions for instruction encoding, sorted by sub-architecture. @@ -8255,7 +8615,7 @@ do_ldst (void) { inst.instruction |= inst.operands[0].reg << 12; if (!inst.operands[1].isreg) - if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) + if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE)) return; encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); check_ldr_r15_aligned (); @@ -8288,7 +8648,7 @@ do_ldstv4 (void) constraint (inst.operands[0].reg == REG_PC, BAD_PC); inst.instruction |= inst.operands[0].reg << 12; if (!inst.operands[1].isreg) - if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) + if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE)) return; encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); } @@ -10832,7 +11192,7 @@ do_t_ldst (void) { if (opcode <= 0xffff) inst.instruction = THUMB_OP32 (opcode); - if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) + if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) return; } if (inst.operands[1].isreg @@ -10938,7 +11298,7 @@ do_t_ldst (void) inst.instruction = THUMB_OP16 (inst.instruction); if (!inst.operands[1].isreg) - if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) + if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE)) return; constraint (!inst.operands[1].preind @@ -13819,197 +14179,6 @@ neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) return FAIL; } -/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits - A, B, C, D. */ - -static int -neon_bits_same_in_bytes (unsigned imm) -{ - return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) - && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) - && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) - && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); -} - -/* For immediate of above form, return 0bABCD. */ - -static unsigned -neon_squash_bits (unsigned imm) -{ - return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) - | ((imm & 0x01000000) >> 21); -} - -/* Compress quarter-float representation to 0b...000 abcdefgh. */ - -static unsigned -neon_qfloat_bits (unsigned imm) -{ - return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); -} - -/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into - the instruction. *OP is passed as the initial value of the op field, and - may be set to a different value depending on the constant (i.e. - "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not - MVN). If the immediate looks like a repeated pattern then also - try smaller element sizes. */ - -static int -neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, - unsigned *immbits, int *op, int size, - enum neon_el_type type) -{ - /* Only permit float immediates (including 0.0/-0.0) if the operand type is - float. */ - if (type == NT_float && !float_p) - return FAIL; - - if (type == NT_float && is_quarter_float (immlo) && immhi == 0) - { - if (size != 32 || *op == 1) - return FAIL; - *immbits = neon_qfloat_bits (immlo); - return 0xf; - } - - if (size == 64) - { - if (neon_bits_same_in_bytes (immhi) - && neon_bits_same_in_bytes (immlo)) - { - if (*op == 1) - return FAIL; - *immbits = (neon_squash_bits (immhi) << 4) - | neon_squash_bits (immlo); - *op = 1; - return 0xe; - } - - if (immhi != immlo) - return FAIL; - } - - if (size >= 32) - { - if (immlo == (immlo & 0x000000ff)) - { - *immbits = immlo; - return 0x0; - } - else if (immlo == (immlo & 0x0000ff00)) - { - *immbits = immlo >> 8; - return 0x2; - } - else if (immlo == (immlo & 0x00ff0000)) - { - *immbits = immlo >> 16; - return 0x4; - } - else if (immlo == (immlo & 0xff000000)) - { - *immbits = immlo >> 24; - return 0x6; - } - else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) - { - *immbits = (immlo >> 8) & 0xff; - return 0xc; - } - else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) - { - *immbits = (immlo >> 16) & 0xff; - return 0xd; - } - - if ((immlo & 0xffff) != (immlo >> 16)) - return FAIL; - immlo &= 0xffff; - } - - if (size >= 16) - { - if (immlo == (immlo & 0x000000ff)) - { - *immbits = immlo; - return 0x8; - } - else if (immlo == (immlo & 0x0000ff00)) - { - *immbits = immlo >> 8; - return 0xa; - } - - if ((immlo & 0xff) != (immlo >> 8)) - return FAIL; - immlo &= 0xff; - } - - if (immlo == (immlo & 0x000000ff)) - { - /* Don't allow MVN with 8-bit immediate. */ - if (*op == 1) - return FAIL; - *immbits = immlo; - return 0xe; - } - - return FAIL; -} - -/* Write immediate bits [7:0] to the following locations: - - |28/24|23 19|18 16|15 4|3 0| - | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| - - This function is used by VMOV/VMVN/VORR/VBIC. */ - -static void -neon_write_immbits (unsigned immbits) -{ - inst.instruction |= immbits & 0xf; - inst.instruction |= ((immbits >> 4) & 0x7) << 16; - inst.instruction |= ((immbits >> 7) & 0x1) << 24; -} - -/* Invert low-order SIZE bits of XHI:XLO. */ - -static void -neon_invert_size (unsigned *xlo, unsigned *xhi, int size) -{ - unsigned immlo = xlo ? *xlo : 0; - unsigned immhi = xhi ? *xhi : 0; - - switch (size) - { - case 8: - immlo = (~immlo) & 0xff; - break; - - case 16: - immlo = (~immlo) & 0xffff; - break; - - case 64: - immhi = (~immhi) & 0xffffffff; - /* fall through. */ - - case 32: - immlo = (~immlo) & 0xffffffff; - break; - - default: - abort (); - } - - if (xlo) - *xlo = immlo; - - if (xhi) - *xhi = immhi; -} - static void do_neon_logic (void) { diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 87b9823..abbd5b9 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,24 @@ +2014-07-08 Jiong Wang + + * gas/arm/ldconst.s: Add test cases for symbol literal. + * gas/arm/ldconst.d: Likewise. + * gas/arm/vldconst.s: Add test cases for vldr. + * gas/arm/thumb2_vpool.s: Likewise. + * gas/arm/vldconst.d: New pattern for little-endian. + * gas/arm/thumb2_vpool.d: Likewise. + * gas/arm/vldconst_be.d: New pattern for big-endian. + * gas/arm/thumb2_vpool_be.d: Likewise. + + * gas/arm/armv8-a+crypto.d: Skip for non-ELF targets. + * gas/arm/armv8-a+fp.d: Likewise. + * gas/arm/armv8-a+simd.d: Likewise. + * gas/arm/armv8-a-barrier-thumb.d: Likewise. + * gas/arm/bl-local-2.d: Likewise. + * gas/arm/ldgesb-bad.d: Likewise. + * gas/arm/ldgesh-bad.d: Likewise. + * gas/arm/thumb2_pool.d: Likewise. + * gas/arm/thumb2_pool.s: Likewise. + 2014-06-17 Jiong Wang * gas/arm/armv8-a-it-bad.s: New check for deprecated sp_inc/dec within diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d index d5b2b4b..453db31 100644 --- a/gas/testsuite/gas/arm/armv8-a+crypto.d +++ b/gas/testsuite/gas/arm/armv8-a+crypto.d @@ -1,5 +1,6 @@ #name: Valid v8-a+cryptov1 #objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d index 6443c4b..f77e742 100644 --- a/gas/testsuite/gas/arm/armv8-a+fp.d +++ b/gas/testsuite/gas/arm/armv8-a+fp.d @@ -1,5 +1,6 @@ #name: Valid v8-a+fp #objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d index 49ef5b6..9d05566 100644 --- a/gas/testsuite/gas/arm/armv8-a+simd.d +++ b/gas/testsuite/gas/arm/armv8-a+simd.d @@ -1,5 +1,6 @@ #name: Valid v8-a+simdv3 #objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d index 42dae15..17c2e93 100644 --- a/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d +++ b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d @@ -2,6 +2,7 @@ #as: -march=armv8-a -mthumb #source: armv8-a-barrier.s #objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/bl-local-2.d b/gas/testsuite/gas/arm/bl-local-2.d index da7a49b..c3a2819 100644 --- a/gas/testsuite/gas/arm/bl-local-2.d +++ b/gas/testsuite/gas/arm/bl-local-2.d @@ -1,5 +1,6 @@ #name: bl local conversion to blx #objdump: -drw --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd #as: diff --git a/gas/testsuite/gas/arm/ldconst.d b/gas/testsuite/gas/arm/ldconst.d index 3d06378..f8c273d 100644 --- a/gas/testsuite/gas/arm/ldconst.d +++ b/gas/testsuite/gas/arm/ldconst.d @@ -1,6 +1,7 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: ARM ldr with immediate constant #as: -mcpu=arm7m -EL +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd .*: +file format .*arm.* @@ -25,3 +26,17 @@ Disassembly of section .text: 0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff 0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*> 0+4c <[^>]*> 0000fff0 ? .* +0+50 <[^>]*> e59f0020 ? ldr r0, \[pc, #32\] ; 0+78 <[^>]*> +0+54 <[^>]*> e59f301c ? ldr r3, \[pc, #28\] ; 0+78 <[^>]*> +0+58 <[^>]*> e59f8018 ? ldr r8, \[pc, #24\] ; 0+78 <[^>]*> +0+5c <[^>]*> e59fb014 ? ldr fp, \[pc, #20\] ; 0+78 <[^>]*> +0+60 <[^>]*> e59fe010 ? ldr lr, \[pc, #16\] ; 0+78 <[^>]*> +0+64 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+7c <[^>]*> +0+68 <[^>]*> e59f300c ? ldr r3, \[pc, #12\] ; 0+7c <[^>]*> +0+6c <[^>]*> e59f8008 ? ldr r8, \[pc, #8\] ; 0+7c <[^>]*> +0+70 <[^>]*> e59fb004 ? ldr fp, \[pc, #4\] ; 0+7c <[^>]*> +0+74 <[^>]*> e51fe000 ? ldr lr, \[pc, #-0\] ; 0+7c <[^>]*> +0+78 <[^>]*> 00000000 .word 0x00000000 + 78: R_ARM_ABS32 ext_symbol +0+7c <[^>]*> 00001000 .word 0x00001000 + 7c: R_ARM_ABS32 ext_symbol diff --git a/gas/testsuite/gas/arm/ldconst.s b/gas/testsuite/gas/arm/ldconst.s index 1b6aca9..d0b5496 100644 --- a/gas/testsuite/gas/arm/ldconst.s +++ b/gas/testsuite/gas/arm/ldconst.s @@ -26,3 +26,14 @@ foo: ldrmi r11, =0xffffff00 ldrmi r11, =0x0000fff0 .pool + + # test symbol literal support. + .macro ldrs const + .irp regindex, 0, 3, 8, 11, 14 + ldr r\regindex, \const + .endr + .endm + + ldrs "=ext_symbol" + ldrs "=ext_symbol + 0x1000" + .pool diff --git a/gas/testsuite/gas/arm/ldgesb-bad.d b/gas/testsuite/gas/arm/ldgesb-bad.d index f11df79..46a3726 100644 --- a/gas/testsuite/gas/arm/ldgesb-bad.d +++ b/gas/testsuite/gas/arm/ldgesb-bad.d @@ -1,3 +1,4 @@ # name: Reject ldsb instructions # as: -march=armv7-a # error-output: ldgesb-bad.l +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd diff --git a/gas/testsuite/gas/arm/ldgesh-bad.d b/gas/testsuite/gas/arm/ldgesh-bad.d index e7c93c3..3dced89 100644 --- a/gas/testsuite/gas/arm/ldgesh-bad.d +++ b/gas/testsuite/gas/arm/ldgesh-bad.d @@ -1,3 +1,4 @@ # name: Reject ldsh instructions # as: -march=armv7-a # error-output: ldgesh-bad.l +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d index 4d6ce44..8f8d881 100644 --- a/gas/testsuite/gas/arm/thumb2_pool.d +++ b/gas/testsuite/gas/arm/thumb2_pool.d @@ -14,3 +14,18 @@ Disassembly of section .text: 0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+> 0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\) 0+014 <[^>]+> 12345678 ? .word 0x12345678 +0+018 <[^>]+> 4907 ldr r1, \[pc, #28\] ; \(00000038 <[^>]+>\) +0+01a <[^>]+> 4c07 ldr r4, \[pc, #28\] ; \(00000038 <[^>]+>\) +0+01c <[^>]+> f8df 9018 ldr.w r9, \[pc, #24\] ; 00000038 <[^>]+> +0+020 <[^>]+> f8df c014 ldr.w ip, \[pc, #20\] ; 00000038 <[^>]+> +0+024 <[^>]+> f8df d010 ldr.w sp, \[pc, #16\] ; 00000038 <[^>]+> +0+028 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0000003c <[^>]+>\) +0+02a <[^>]+> 4c04 ldr r4, \[pc, #16\] ; \(0000003c <[^>]+>\) +0+02c <[^>]+> f8df 900c ldr.w r9, \[pc, #12\] ; 0000003c <[^>]+> +0+030 <[^>]+> f8df c008 ldr.w ip, \[pc, #8\] ; 0000003c <[^>]+> +0+034 <[^>]+> f8df d004 ldr.w sp, \[pc, #4\] ; 0000003c <[^>]+> +0+038 <[^>]+> 00000000 .word 0x00000000 + 38: R_ARM_ABS32 ext_symbol +0+03c <[^>]+> 00001000 .word 0x00001000 + 3c: R_ARM_ABS32 ext_symbol + diff --git a/gas/testsuite/gas/arm/thumb2_pool.s b/gas/testsuite/gas/arm/thumb2_pool.s index 844e77e..92c0fe9 100644 --- a/gas/testsuite/gas/arm/thumb2_pool.s +++ b/gas/testsuite/gas/arm/thumb2_pool.s @@ -11,3 +11,14 @@ thumb2_ldr: ldr.w r5, =0x12345678 ldr r1, =0x12345678 .pool + + # test symbol literal support. + .macro ldrs const + .irp regindex, 1, 4, 9, 12, 13 + ldr r\regindex, \const + .endr + .endm + + ldrs "=ext_symbol" + ldrs "=ext_symbol + 0x1000" + .pool diff --git a/gas/testsuite/gas/arm/thumb2_vpool.d b/gas/testsuite/gas/arm/thumb2_vpool.d new file mode 100644 index 0000000..5a8cb6f --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_vpool.d @@ -0,0 +1,169 @@ +# as: -march=armv6t2 -EL +# objdump: -dr --prefix-addresses --show-raw-insn +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Thumb2 vldr with immediate constant + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 +00000004 ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 +00000008 ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 +0000000c eddf fa0c vldr s31, \[pc, #48\] ; 00000040 +00000010 ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 +00000014 ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 +00000018 ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 +0000001c eddf fa09 vldr s31, \[pc, #36\] ; 00000044 +00000020 ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 +00000024 ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 +00000028 ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 +0000002c eddf fa06 vldr s31, \[pc, #24\] ; 00000048 +00000030 ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c +00000034 ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c +00000038 ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c +0000003c eddf fa03 vldr s31, \[pc, #12\] ; 0000004c +00000040 00000000 .word 0x00000000 +00000044 ff000000 .word 0xff000000 +00000048 ffffffff .word 0xffffffff +0000004c 0fff0000 .word 0x0fff0000 +00000050 ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 +00000054 ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 +00000058 ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 +0000005c eddf fa0c vldr s31, \[pc, #48\] ; 00000090 +00000060 ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 +00000064 ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 +00000068 ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 +0000006c eddf fa09 vldr s31, \[pc, #36\] ; 00000094 +00000070 ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 +00000074 ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 +00000078 ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 +0000007c eddf fa06 vldr s31, \[pc, #24\] ; 00000098 +00000080 ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c +00000084 ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c +00000088 ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c +0000008c eddf fa03 vldr s31, \[pc, #12\] ; 0000009c +00000090 00000000 .word 0x00000000 +00000094 00ff0000 .word 0x00ff0000 +00000098 ff00ffff .word 0xff00ffff +0000009c 00fff000 .word 0x00fff000 +000000a0 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +000000a4 ef80 ee30 vmov.i64 d14, #0x0000000000000000 +000000a8 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +000000ac efc0 fe30 vmov.i64 d31, #0x0000000000000000 +000000b0 ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 +000000b4 ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 +000000b8 eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 +000000bc eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 +000000c0 ff87 0e3f vmov.i64 d0, #0xffffffffffffffff +000000c4 ff87 ee3f vmov.i64 d14, #0xffffffffffffffff +000000c8 ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff +000000cc ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff +000000d0 ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 +000000d4 ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 +000000d8 eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 +000000dc eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 +000000e0 ca000000 .word 0xca000000 +000000e4 00000000 .word 0x00000000 +000000e8 0fff0000 .word 0x0fff0000 +000000ec 00000000 .word 0x00000000 +000000f0 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +000000f4 ef80 ee30 vmov.i64 d14, #0x0000000000000000 +000000f8 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +000000fc efc0 fe30 vmov.i64 d31, #0x0000000000000000 +00000100 ef80 0e34 vmov.i64 d0, #0x0000000000ff0000 +00000104 ef80 ee34 vmov.i64 d14, #0x0000000000ff0000 +00000108 efc0 ce34 vmov.i64 d28, #0x0000000000ff0000 +0000010c efc0 fe34 vmov.i64 d31, #0x0000000000ff0000 +00000110 ef80 0e39 vmov.i64 d0, #0x00000000ff0000ff +00000114 ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff +00000118 efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff +0000011c efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff +00000120 ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 +00000124 ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 +00000128 eddf cb01 vldr d28, \[pc, #4\] ; 00000130 +0000012c eddf fb00 vldr d31, \[pc\] ; 00000130 +00000130 00fff000 .word 0x00fff000 +00000134 00000000 .word 0x00000000 +00000138 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +0000013c ef80 ee30 vmov.i64 d14, #0x0000000000000000 +00000140 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +00000144 efc0 fe30 vmov.i64 d31, #0x0000000000000000 +00000148 ff80 0e30 vmov.i64 d0, #0xff00000000000000 +0000014c ff80 ee30 vmov.i64 d14, #0xff00000000000000 +00000150 ffc0 ce30 vmov.i64 d28, #0xff00000000000000 +00000154 ffc0 fe30 vmov.i64 d31, #0xff00000000000000 +00000158 ff87 0e3f vmov.i64 d0, #0xffffffffffffffff +0000015c ff87 ee3f vmov.i64 d14, #0xffffffffffffffff +00000160 ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff +00000164 ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff +00000168 ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 +0000016c ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 +00000170 eddf cb01 vldr d28, \[pc, #4\] ; 00000178 +00000174 eddf fb00 vldr d31, \[pc\] ; 00000178 +00000178 00000000 .word 0x00000000 +0000017c 0fff0000 .word 0x0fff0000 +00000180 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +00000184 ef80 ee30 vmov.i64 d14, #0x0000000000000000 +00000188 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +0000018c efc0 fe30 vmov.i64 d31, #0x0000000000000000 +00000190 ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 +00000194 ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 +00000198 eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 +0000019c eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 +000001a0 ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 +000001a4 ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 +000001a8 eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 +000001ac eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 +000001b0 ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 +000001b4 ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 +000001b8 eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 +000001bc eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 +000001c0 00000000 .word 0x00000000 +000001c4 000ff000 .word 0x000ff000 +000001c8 f0000000 .word 0xf0000000 +000001cc 0ff00fff .word 0x0ff00fff +000001d0 ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 + \.\.\. +000001dc 0000fff0 .word 0x0000fff0 +000001e0 f101 0000 add.w r0, r1, #0 +000001e4 ed9f 1b00 vldr d1, \[pc\] ; 000001e8 +000001e8 00000000 .word 0x00000000 +000001ec 0000fff0 .word 0x0000fff0 +000001f0 ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 +000001f4 ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 +000001f8 ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 +000001fc ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 +00000200 ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 +00000204 ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 +00000208 ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 +0000020c ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 +00000210 ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 +00000214 ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 +00000218 ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 +0000021c ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 +00000220 eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c +00000224 ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 +00000228 eddf 7a04 vldr s15, \[pc, #16\] ; 0000023c +0000022c eddf 0b12 vldr d16, \[pc, #72\] ; 00000278 +00000230 eddf 1b13 vldr d17, \[pc, #76\] ; 00000280 + \.\.\. +0000023c 0000fff0 .word 0x0000fff0 +00000240 ff000000 .word 0xff000000 +00000244 ff000001 .word 0xff000001 +00000248 00000001 .word 0x00000001 +0000024c 0000fff0 .word 0x0000fff0 +00000250 00000002 .word 0x00000002 +00000254 0000fff0 .word 0x0000fff0 +00000258 00000003 .word 0x00000003 +0000025c 0000fff0 .word 0x0000fff0 +00000260 ff000002 .word 0xff000002 +00000264 ff000003 .word 0xff000003 +00000268 00000004 .word 0x00000004 +0000026c 0000fff0 .word 0x0000fff0 +00000270 00000005 .word 0x00000005 +00000274 0000fff0 .word 0x0000fff0 +00000278 ff000004 .word 0xff000004 +0000027c ff000005 .word 0xff000005 +00000280 0000fff0 .word 0x0000fff0 +00000284 ff000004 .word 0xff000004 diff --git a/gas/testsuite/gas/arm/thumb2_vpool.s b/gas/testsuite/gas/arm/thumb2_vpool.s new file mode 100644 index 0000000..efbbc77 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_vpool.s @@ -0,0 +1,95 @@ + .text + .fpu neon + .thumb + .syntax unified + .thumb_func +thumb2_ldr: + .macro vlxr regtype const + .irp regindex, 0, 14, 28, 31 + vldr \regtype\regindex, \const + .endr + .endm + # Thumb-2 support vldr literal pool also. + vlxr s "=0" + vlxr s "=0xff000000" + vlxr s "=-1" + vlxr s "=0x0fff0000" + .pool + + vlxr s "=0" + vlxr s "=0x00ff0000" + vlxr s "=0xff00ffff" + vlxr s "=0x00fff000" + .pool + + vlxr d "=0" + vlxr d "=0xca000000" + vlxr d "=-1" + vlxr d "=0x0fff0000" + .pool + + vlxr d "=0" + vlxr d "=0x00ff0000" + vlxr d "=0xff0000ff" + vlxr d "=0x00fff000" + .pool + + vlxr d "=0" + vlxr d "=0xff00000000000000" + vlxr d "=-1" + vlxr d "=0x0fff000000000000" + .pool + + vlxr d "=0" + vlxr d "=0x00ff00000000000" + vlxr d "=0xff00ffff0000000" + vlxr d "=0xff00ffff0000000" + .pool + + # pool should be aligned to 8-byte. + .p2align 3 + vldr d1, =0x0000fff000000000 + .pool + + # no error when code is align already. + .p2align 3 + add r0, r1, #0 + vldr d1, =0x0000fff000000000 + .pool + + .p2align 3 + vldr d1, =0x0000fff000000000 + vldr s2, =0xff000000 + # padding A + vldr d3, =0x0000fff000000001 + # reuse padding slot A + vldr s4, =0xff000001 + # reuse d3 + vldr d5, =0x0000fff000000001 + # new 8-byte entry + vldr d6, =0x0000fff000000002 + # new 8-byte entry + vldr d7, =0x0000fff000000003 + # new 4-byte entry + vldr s8, =0xff000002 + # padding B + vldr d9, =0x0000fff000000004 + # reuse padding slot B + vldr s10, =0xff000003 + # new 8-byte entry + vldr d11, =0x0000fff000000005 + # new 4 entry + vldr s12, =0xff000004 + # new 4 entry + vldr s13, =0xff000005 + # reuse value of s4 in pool + vldr s14, =0xff000001 + # reuse high part of d1 in pool + vldr s15, =0x0000fff0 + # 8-byte entry reuse two 4-byte entries. + # d16 reuse s12, s13 + vldr d16, =0xff000005ff000004 + # d17 should not reuse high part of d11 and s12. + # because the it's align 8-byte aligned. + vldr d17, =0xff0000040000fff0 + .pool diff --git a/gas/testsuite/gas/arm/thumb2_vpool_be.d b/gas/testsuite/gas/arm/thumb2_vpool_be.d new file mode 100644 index 0000000..816cddc --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_vpool_be.d @@ -0,0 +1,176 @@ +# as: -march=armv6t2 -mbig-endian +# objdump: -dr --prefix-addresses --show-raw-insn +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Thumb2 vldr with immediate constant +#source: thumb2_vpool.s + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 +00000004 ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 +00000008 ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 +0000000c eddf fa0c vldr s31, \[pc, #48\] ; 00000040 +00000010 ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 +00000014 ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 +00000018 ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 +0000001c eddf fa09 vldr s31, \[pc, #36\] ; 00000044 +00000020 ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 +00000024 ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 +00000028 ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 +0000002c eddf fa06 vldr s31, \[pc, #24\] ; 00000048 +00000030 ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c +00000034 ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c +00000038 ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c +0000003c eddf fa03 vldr s31, \[pc, #12\] ; 0000004c +00000040 00000000 .word 0x00000000 +00000044 ff000000 .word 0xff000000 +00000048 ffffffff .word 0xffffffff +0000004c 0fff0000 .word 0x0fff0000 +00000050 ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 +00000054 ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 +00000058 ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 +0000005c eddf fa0c vldr s31, \[pc, #48\] ; 00000090 +00000060 ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 +00000064 ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 +00000068 ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 +0000006c eddf fa09 vldr s31, \[pc, #36\] ; 00000094 +00000070 ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 +00000074 ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 +00000078 ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 +0000007c eddf fa06 vldr s31, \[pc, #24\] ; 00000098 +00000080 ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c +00000084 ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c +00000088 ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c +0000008c eddf fa03 vldr s31, \[pc, #12\] ; 0000009c +00000090 00000000 .word 0x00000000 +00000094 00ff0000 .word 0x00ff0000 +00000098 ff00ffff .word 0xff00ffff +0000009c 00fff000 .word 0x00fff000 +000000a0 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +000000a4 ef80 ee30 vmov.i64 d14, #0x0000000000000000 +000000a8 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +000000ac efc0 fe30 vmov.i64 d31, #0x0000000000000000 +000000b0 ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 +000000b4 ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 +000000b8 eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 +000000bc eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 +000000c0 ff87 0e3f vmov.i64 d0, #0xffffffffffffffff +000000c4 ff87 ee3f vmov.i64 d14, #0xffffffffffffffff +000000c8 ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff +000000cc ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff +000000d0 ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 +000000d4 ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 +000000d8 eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 +000000dc eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 +000000e0 00000000 .word 0x00000000 +000000e4 ca000000 .word 0xca000000 +000000e8 00000000 .word 0x00000000 +000000ec 0fff0000 .word 0x0fff0000 +000000f0 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +000000f4 ef80 ee30 vmov.i64 d14, #0x0000000000000000 +000000f8 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +000000fc efc0 fe30 vmov.i64 d31, #0x0000000000000000 +00000100 ef80 0e34 vmov.i64 d0, #0x0000000000ff0000 +00000104 ef80 ee34 vmov.i64 d14, #0x0000000000ff0000 +00000108 efc0 ce34 vmov.i64 d28, #0x0000000000ff0000 +0000010c efc0 fe34 vmov.i64 d31, #0x0000000000ff0000 +00000110 ef80 0e39 vmov.i64 d0, #0x00000000ff0000ff +00000114 ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff +00000118 efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff +0000011c efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff +00000120 ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 +00000124 ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 +00000128 eddf cb01 vldr d28, \[pc, #4\] ; 00000130 +0000012c eddf fb00 vldr d31, \[pc\] ; 00000130 +00000130 00000000 .word 0x00000000 +00000134 00fff000 .word 0x00fff000 +00000138 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +0000013c ef80 ee30 vmov.i64 d14, #0x0000000000000000 +00000140 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +00000144 efc0 fe30 vmov.i64 d31, #0x0000000000000000 +00000148 ff80 0e30 vmov.i64 d0, #0xff00000000000000 +0000014c ff80 ee30 vmov.i64 d14, #0xff00000000000000 +00000150 ffc0 ce30 vmov.i64 d28, #0xff00000000000000 +00000154 ffc0 fe30 vmov.i64 d31, #0xff00000000000000 +00000158 ff87 0e3f vmov.i64 d0, #0xffffffffffffffff +0000015c ff87 ee3f vmov.i64 d14, #0xffffffffffffffff +00000160 ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff +00000164 ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff +00000168 ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 +0000016c ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 +00000170 eddf cb01 vldr d28, \[pc, #4\] ; 00000178 +00000174 eddf fb00 vldr d31, \[pc\] ; 00000178 +00000178 0fff0000 .word 0x0fff0000 +0000017c 00000000 .word 0x00000000 +00000180 ef80 0e30 vmov.i64 d0, #0x0000000000000000 +00000184 ef80 ee30 vmov.i64 d14, #0x0000000000000000 +00000188 efc0 ce30 vmov.i64 d28, #0x0000000000000000 +0000018c efc0 fe30 vmov.i64 d31, #0x0000000000000000 +00000190 ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 +00000194 ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 +00000198 eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 +0000019c eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 +000001a0 ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 +000001a4 ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 +000001a8 eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 +000001ac eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 +000001b0 ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 +000001b4 ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 +000001b8 eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 +000001bc eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 +000001c0 000ff000 .word 0x000ff000 +000001c4 00000000 .word 0x00000000 +000001c8 0ff00fff .word 0x0ff00fff +000001cc f0000000 .word 0xf0000000 +000001d0 ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 +000001d4 0000 movs r0, r0 +000001d6 0000 movs r0, r0 +000001d8 0000fff0 .word 0x0000fff0 +000001dc 00000000 .word 0x00000000 +000001e0 f101 0000 add.w r0, r1, #0 +000001e4 ed9f 1b00 vldr d1, \[pc\] ; 000001e8 +000001e8 0000fff0 .word 0x0000fff0 +000001ec 00000000 .word 0x00000000 +000001f0 ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 +000001f4 ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 +000001f8 ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 +000001fc ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 +00000200 ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 +00000204 ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 +00000208 ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 +0000020c ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 +00000210 ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 +00000214 ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 +00000218 ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 +0000021c ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 +00000220 eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c +00000224 ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 +00000228 eddf 7a03 vldr s15, \[pc, #12\] ; 00000238 +0000022c eddf 0b14 vldr d16, \[pc, #80\] ; 00000280 +00000230 eddf 1b15 vldr d17, \[pc, #84\] ; 00000288 +00000234 0000 movs r0, r0 +00000236 0000 movs r0, r0 +00000238 0000fff0 .word 0x0000fff0 +0000023c 00000000 .word 0x00000000 +00000240 ff000000 .word 0xff000000 +00000244 ff000001 .word 0xff000001 +00000248 0000fff0 .word 0x0000fff0 +0000024c 00000001 .word 0x00000001 +00000250 0000fff0 .word 0x0000fff0 +00000254 00000002 .word 0x00000002 +00000258 0000fff0 .word 0x0000fff0 +0000025c 00000003 .word 0x00000003 +00000260 ff000002 .word 0xff000002 +00000264 ff000003 .word 0xff000003 +00000268 0000fff0 .word 0x0000fff0 +0000026c 00000004 .word 0x00000004 +00000270 0000fff0 .word 0x0000fff0 +00000274 00000005 .word 0x00000005 +00000278 ff000004 .word 0xff000004 +0000027c ff000005 .word 0xff000005 +00000280 ff000005 .word 0xff000005 +00000284 ff000004 .word 0xff000004 +00000288 ff000004 .word 0xff000004 +0000028c 0000fff0 .word 0x0000fff0 diff --git a/gas/testsuite/gas/arm/vldconst.d b/gas/testsuite/gas/arm/vldconst.d new file mode 100644 index 0000000..221f3e3 --- /dev/null +++ b/gas/testsuite/gas/arm/vldconst.d @@ -0,0 +1,280 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM vldr with immediate constant +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#as: -mcpu=arm7m -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 +00000004 ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 +00000008 ed9fea0c vldr s28, \[pc, #48\] ; 00000040 +0000000c eddffa0b vldr s31, \[pc, #44\] ; 00000040 +00000010 ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 +00000014 ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 +00000018 ed9fea09 vldr s28, \[pc, #36\] ; 00000044 +0000001c eddffa08 vldr s31, \[pc, #32\] ; 00000044 +00000020 ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 +00000024 ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 +00000028 ed9fea06 vldr s28, \[pc, #24\] ; 00000048 +0000002c eddffa05 vldr s31, \[pc, #20\] ; 00000048 +00000030 ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c +00000034 ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c +00000038 ed9fea03 vldr s28, \[pc, #12\] ; 0000004c +0000003c eddffa02 vldr s31, \[pc, #8\] ; 0000004c +00000040 00000000 .word 0x00000000 +00000044 ff000000 .word 0xff000000 +00000048 ffffffff .word 0xffffffff +0000004c 0fff0000 .word 0x0fff0000 +00000050 ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 +00000054 ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 +00000058 ed9fea0c vldr s28, \[pc, #48\] ; 00000090 +0000005c eddffa0b vldr s31, \[pc, #44\] ; 00000090 +00000060 ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 +00000064 ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 +00000068 ed9fea09 vldr s28, \[pc, #36\] ; 00000094 +0000006c eddffa08 vldr s31, \[pc, #32\] ; 00000094 +00000070 ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 +00000074 ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 +00000078 ed9fea06 vldr s28, \[pc, #24\] ; 00000098 +0000007c eddffa05 vldr s31, \[pc, #20\] ; 00000098 +00000080 ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c +00000084 ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c +00000088 ed9fea03 vldr s28, \[pc, #12\] ; 0000009c +0000008c eddffa02 vldr s31, \[pc, #8\] ; 0000009c +00000090 00000000 .word 0x00000000 +00000094 00ff0000 .word 0x00ff0000 +00000098 ff00ffff .word 0xff00ffff +0000009c 00fff000 .word 0x00fff000 +000000a0 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 +000000a4 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 +000000a8 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 +000000ac 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 +000000b0 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 +000000b4 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 +000000b8 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 +000000bc 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 +000000c0 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 +000000c4 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 +000000c8 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 +000000cc 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 +000000d0 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec +000000d4 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec +000000d8 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec +000000dc 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec +000000e0 00000000 .word 0x00000000 +000000e4 0000ff00 .word 0x0000ff00 +000000e8 ffff00ff .word 0xffff00ff +000000ec 000fff00 .word 0x000fff00 +000000f0 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 +000000f4 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 +000000f8 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 +000000fc 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 +00000100 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 +00000104 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 +00000108 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 +0000010c 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 +00000110 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 +00000114 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 +00000118 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 +0000011c 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 +00000120 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c +00000124 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c +00000128 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c +0000012c 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c +00000130 00000000 .word 0x00000000 +00000134 000000ff .word 0x000000ff +00000138 ffffff00 .word 0xffffff00 +0000013c 0000fff0 .word 0x0000fff0 +00000140 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000144 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000148 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000014c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000150 ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 +00000154 ed9feb09 vldr d14, \[pc, #36\] ; 00000180 +00000158 eddfcb08 vldr d28, \[pc, #32\] ; 00000180 +0000015c eddffb07 vldr d31, \[pc, #28\] ; 00000180 +00000160 f3870e3f vmov.i64 d0, #0xffffffffffffffff +00000164 f387ee3f vmov.i64 d14, #0xffffffffffffffff +00000168 f3c7ce3f vmov.i64 d28, #0xffffffffffffffff +0000016c f3c7fe3f vmov.i64 d31, #0xffffffffffffffff +00000170 ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 +00000174 ed9feb03 vldr d14, \[pc, #12\] ; 00000188 +00000178 eddfcb02 vldr d28, \[pc, #8\] ; 00000188 +0000017c eddffb01 vldr d31, \[pc, #4\] ; 00000188 +00000180 ca000000 .word 0xca000000 +00000184 00000000 .word 0x00000000 +00000188 0fff0000 .word 0x0fff0000 +0000018c 00000000 .word 0x00000000 +00000190 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000194 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000198 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000019c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +000001a0 f2800e34 vmov.i64 d0, #0x0000000000ff0000 +000001a4 f280ee34 vmov.i64 d14, #0x0000000000ff0000 +000001a8 f2c0ce34 vmov.i64 d28, #0x0000000000ff0000 +000001ac f2c0fe34 vmov.i64 d31, #0x0000000000ff0000 +000001b0 f2800e39 vmov.i64 d0, #0x00000000ff0000ff +000001b4 f280ee39 vmov.i64 d14, #0x00000000ff0000ff +000001b8 f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff +000001bc f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff +000001c0 ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 +000001c4 ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 +000001c8 eddfcb00 vldr d28, \[pc\] ; 000001d0 +000001cc ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 +000001d0 00fff000 .word 0x00fff000 +000001d4 00000000 .word 0x00000000 +000001d8 f2800e30 vmov.i64 d0, #0x0000000000000000 +000001dc f280ee30 vmov.i64 d14, #0x0000000000000000 +000001e0 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +000001e4 f2c0fe30 vmov.i64 d31, #0x0000000000000000 +000001e8 f2800e32 vmov.i64 d0, #0x000000000000ff00 +000001ec f280ee32 vmov.i64 d14, #0x000000000000ff00 +000001f0 f2c0ce32 vmov.i64 d28, #0x000000000000ff00 +000001f4 f2c0fe32 vmov.i64 d31, #0x000000000000ff00 +000001f8 f2800e3d vmov.i64 d0, #0x00000000ffff00ff +000001fc f280ee3d vmov.i64 d14, #0x00000000ffff00ff +00000200 f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff +00000204 f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff +00000208 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 +0000020c 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 +00000210 0ddfcb00 vldreq d28, \[pc\] ; 00000218 +00000214 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 +00000218 000fff00 .word 0x000fff00 +0000021c 00000000 .word 0x00000000 +00000220 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000224 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000228 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000022c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000230 f2800e31 vmov.i64 d0, #0x00000000000000ff +00000234 f280ee31 vmov.i64 d14, #0x00000000000000ff +00000238 f2c0ce31 vmov.i64 d28, #0x00000000000000ff +0000023c f2c0fe31 vmov.i64 d31, #0x00000000000000ff +00000240 f2800e3e vmov.i64 d0, #0x00000000ffffff00 +00000244 f280ee3e vmov.i64 d14, #0x00000000ffffff00 +00000248 f2c0ce3e vmov.i64 d28, #0x00000000ffffff00 +0000024c f2c0fe3e vmov.i64 d31, #0x00000000ffffff00 +00000250 f2800e33 vmov.i64 d0, #0x000000000000ffff +00000254 f280ee33 vmov.i64 d14, #0x000000000000ffff +00000258 f2c0ce33 vmov.i64 d28, #0x000000000000ffff +0000025c f2c0fe33 vmov.i64 d31, #0x000000000000ffff +00000260 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000264 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000268 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000026c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000270 f3800e30 vmov.i64 d0, #0xff00000000000000 +00000274 f380ee30 vmov.i64 d14, #0xff00000000000000 +00000278 f3c0ce30 vmov.i64 d28, #0xff00000000000000 +0000027c f3c0fe30 vmov.i64 d31, #0xff00000000000000 +00000280 f3870e3f vmov.i64 d0, #0xffffffffffffffff +00000284 f387ee3f vmov.i64 d14, #0xffffffffffffffff +00000288 f3c7ce3f vmov.i64 d28, #0xffffffffffffffff +0000028c f3c7fe3f vmov.i64 d31, #0xffffffffffffffff +00000290 ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 +00000294 ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 +00000298 eddfcb00 vldr d28, \[pc\] ; 000002a0 +0000029c ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 +000002a0 00000000 .word 0x00000000 +000002a4 0fff0000 .word 0x0fff0000 +000002a8 f2800e30 vmov.i64 d0, #0x0000000000000000 +000002ac f280ee30 vmov.i64 d14, #0x0000000000000000 +000002b0 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +000002b4 f2c0fe30 vmov.i64 d31, #0x0000000000000000 +000002b8 ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 +000002bc ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 +000002c0 eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 +000002c4 eddffb07 vldr d31, \[pc, #28\] ; 000002e8 +000002c8 ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 +000002cc ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 +000002d0 eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 +000002d4 eddffb05 vldr d31, \[pc, #20\] ; 000002f0 +000002d8 ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 +000002dc ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 +000002e0 eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 +000002e4 eddffb03 vldr d31, \[pc, #12\] ; 000002f8 +000002e8 00000000 .word 0x00000000 +000002ec 000ff000 .word 0x000ff000 +000002f0 f0000000 .word 0xf0000000 +000002f4 0ff00fff .word 0x0ff00fff +000002f8 00000000 .word 0x00000000 +000002fc 000fff00 .word 0x000fff00 +00000300 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000304 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000308 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000030c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000310 f2820e30 vmov.i64 d0, #0x0000ff0000000000 +00000314 f282ee30 vmov.i64 d14, #0x0000ff0000000000 +00000318 f2c2ce30 vmov.i64 d28, #0x0000ff0000000000 +0000031c f2c2fe30 vmov.i64 d31, #0x0000ff0000000000 +00000320 f3850e30 vmov.i64 d0, #0xffff00ff00000000 +00000324 f385ee30 vmov.i64 d14, #0xffff00ff00000000 +00000328 f3c5ce30 vmov.i64 d28, #0xffff00ff00000000 +0000032c f3c5fe30 vmov.i64 d31, #0xffff00ff00000000 +00000330 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 +00000334 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 +00000338 0ddfcb00 vldreq d28, \[pc\] ; 00000340 +0000033c 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 +00000340 00000000 .word 0x00000000 +00000344 000fff00 .word 0x000fff00 +00000348 f2800e30 vmov.i64 d0, #0x0000000000000000 +0000034c f280ee30 vmov.i64 d14, #0x0000000000000000 +00000350 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +00000354 f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000358 f2810e30 vmov.i64 d0, #0x000000ff00000000 +0000035c f281ee30 vmov.i64 d14, #0x000000ff00000000 +00000360 f2c1ce30 vmov.i64 d28, #0x000000ff00000000 +00000364 f2c1fe30 vmov.i64 d31, #0x000000ff00000000 +00000368 f3860e30 vmov.i64 d0, #0xffffff0000000000 +0000036c f386ee30 vmov.i64 d14, #0xffffff0000000000 +00000370 f3c6ce30 vmov.i64 d28, #0xffffff0000000000 +00000374 f3c6fe30 vmov.i64 d31, #0xffffff0000000000 +00000378 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 +0000037c 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 +00000380 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 +00000384 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 +00000388 00000000 .word 0x00000000 +0000038c 0000fff0 .word 0x0000fff0 +00000390 ed9f1b00 vldr d1, \[pc\] ; 00000398 + \.\.\. +0000039c 0000fff0 .word 0x0000fff0 +000003a0 e2810000 add r0, r1, #0 +000003a4 ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 +000003a8 00000000 .word 0x00000000 +000003ac 0000fff0 .word 0x0000fff0 +000003b0 ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 +000003b4 ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 +000003b8 ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 +000003bc ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 +000003c0 ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 +000003c4 ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 +000003c8 ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 +000003cc ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 +000003d0 ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 +000003d4 ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 +000003d8 ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 +000003dc ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 +000003e0 eddf6a15 vldr s13, \[pc, #84\] ; 0000043c +000003e4 ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 +000003e8 eddf7a03 vldr s15, \[pc, #12\] ; 000003fc +000003ec eddf0b11 vldr d16, \[pc, #68\] ; 00000438 +000003f0 eddf1b12 vldr d17, \[pc, #72\] ; 00000440 + \.\.\. +000003fc 0000fff0 .word 0x0000fff0 +00000400 ff000000 .word 0xff000000 +00000404 ff000001 .word 0xff000001 +00000408 00000001 .word 0x00000001 +0000040c 0000fff0 .word 0x0000fff0 +00000410 00000002 .word 0x00000002 +00000414 0000fff0 .word 0x0000fff0 +00000418 00000003 .word 0x00000003 +0000041c 0000fff0 .word 0x0000fff0 +00000420 ff000002 .word 0xff000002 +00000424 ff000003 .word 0xff000003 +00000428 00000004 .word 0x00000004 +0000042c 0000fff0 .word 0x0000fff0 +00000430 00000005 .word 0x00000005 +00000434 0000fff0 .word 0x0000fff0 +00000438 ff000004 .word 0xff000004 +0000043c ff000005 .word 0xff000005 +00000440 0000fff0 .word 0x0000fff0 +00000444 ff000004 .word 0xff000004 diff --git a/gas/testsuite/gas/arm/vldconst.s b/gas/testsuite/gas/arm/vldconst.s new file mode 100644 index 0000000..8bb6ee4 --- /dev/null +++ b/gas/testsuite/gas/arm/vldconst.s @@ -0,0 +1,146 @@ +@ Test file for ARM/GAS -- vldr reg, =... expressions. +.fpu neon +.text +.align +foo: + # test both low and high index of the + # Advanced SIMD and Floating-point reg. + .macro vlxr regtype const + .irp regindex, 0, 14, 28, 31 + vldr \regtype\regindex, \const + .endr + .endm + + .macro vlxreq regtype const + .irp regindex, 0, 14, 28, 31 + vldreq \regtype\regindex, \const + .endr + .endm + + .macro vlxrmi regtype const + .irp regindex, 0, 14, 28, 31 + vldrmi \regtype\regindex, \const + .endr + .endm + + vlxr s "=0" + vlxr s "=0xff000000" + vlxr s "=-1" + vlxr s "=0x0fff0000" + .pool + + vlxr s "=0" + vlxr s "=0x00ff0000" + vlxr s "=0xff00ffff" + vlxr s "=0x00fff000" + .pool + + vlxreq s "=0" + vlxreq s "=0x0000ff00" + vlxreq s "=0xffff00ff" + vlxreq s "=0x000fff00" + .pool + + vlxrmi s "=0" + vlxrmi s "=0x000000ff" + vlxrmi s "=0xffffff00" + vlxrmi s "=0x0000fff0" + .pool + + vlxr d "=0" + vlxr d "=0xca000000" + vlxr d "=-1" + vlxr d "=0x0fff0000" + .pool + + vlxr d "=0" + vlxr d "=0x00ff0000" + vlxr d "=0xff0000ff" + vlxr d "=0x00fff000" + .pool + + vlxreq d "=0" + vlxreq d "=0x0000ff00" + vlxreq d "=0xffff00ff" + vlxreq d "=0x000fff00" + .pool + + vlxrmi d "=0" + vlxrmi d "=0x000000ff" + vlxrmi d "=0xffffff00" + vlxrmi d "=0x0000ffff" + .pool + + vlxr d "=0" + vlxr d "=0xff00000000000000" + vlxr d "=-1" + vlxr d "=0x0fff000000000000" + .pool + + vlxr d "=0" + vlxr d "=0x00ff00000000000" + vlxr d "=0xff00ffff0000000" + vlxr d "=0x00fff0000000000" + .pool + + vlxreq d "=0" + vlxreq d "=0x0000ff0000000000" + vlxreq d "=0xffff00ff00000000" + vlxreq d "=0x000fff0000000000" + .pool + + vlxrmi d "=0" + vlxrmi d "=0x000000ff00000000" + vlxrmi d "=0xffffff0000000000" + vlxrmi d "=0x0000fff000000000" + .pool + + # pool should be aligned to 8-byte. + .p2align 3 + vldr d1, =0x0000fff000000000 + .pool + + # no error when code is align already. + .p2align 3 + add r0, r1, #0 + vldr d1, =0x0000fff000000000 + .pool + + .p2align 3 + vldr d1, =0x0000fff000000000 + vldr s2, =0xff000000 + # padding A + vldr d3, =0x0000fff000000001 + # reuse padding slot A + vldr s4, =0xff000001 + # reuse d3 + vldr d5, =0x0000fff000000001 + # new 8-byte entry + vldr d6, =0x0000fff000000002 + # new 8-byte entry + vldr d7, =0x0000fff000000003 + # new 4-byte entry + vldr s8, =0xff000002 + # padding B + vldr d9, =0x0000fff000000004 + # reuse padding slot B + vldr s10, =0xff000003 + # new 8-byte entry + vldr d11, =0x0000fff000000005 + # new 4 entry + vldr s12, =0xff000004 + # new 4 entry + vldr s13, =0xff000005 + # reuse value of s4 in pool + vldr s14, =0xff000001 + # reuse high part of d1 in pool + vldr s15, =0x0000fff0 + # 8-byte entry reuse two 4-byte entries. + # this reuse should only happen for + # little-endian + # d16 reuse s12, s13 + vldr d16, =0xff000005ff000004 + # d17 should not reuse high part of d11 and s12. + # because the it's align 8-byte aligned. + vldr d17, =0xff0000040000fff0 + .pool diff --git a/gas/testsuite/gas/arm/vldconst_be.d b/gas/testsuite/gas/arm/vldconst_be.d new file mode 100644 index 0000000..cf3dbf9 --- /dev/null +++ b/gas/testsuite/gas/arm/vldconst_be.d @@ -0,0 +1,285 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM vldr with immediate constant (Big Endian) +#as: -mcpu=arm7m -mbig-endian +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#source: vldconst.s + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 +00000004 ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 +00000008 ed9fea0c vldr s28, \[pc, #48\] ; 00000040 +0000000c eddffa0b vldr s31, \[pc, #44\] ; 00000040 +00000010 ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 +00000014 ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 +00000018 ed9fea09 vldr s28, \[pc, #36\] ; 00000044 +0000001c eddffa08 vldr s31, \[pc, #32\] ; 00000044 +00000020 ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 +00000024 ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 +00000028 ed9fea06 vldr s28, \[pc, #24\] ; 00000048 +0000002c eddffa05 vldr s31, \[pc, #20\] ; 00000048 +00000030 ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c +00000034 ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c +00000038 ed9fea03 vldr s28, \[pc, #12\] ; 0000004c +0000003c eddffa02 vldr s31, \[pc, #8\] ; 0000004c +00000040 00000000 .word 0x00000000 +00000044 ff000000 .word 0xff000000 +00000048 ffffffff .word 0xffffffff +0000004c 0fff0000 .word 0x0fff0000 +00000050 ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 +00000054 ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 +00000058 ed9fea0c vldr s28, \[pc, #48\] ; 00000090 +0000005c eddffa0b vldr s31, \[pc, #44\] ; 00000090 +00000060 ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 +00000064 ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 +00000068 ed9fea09 vldr s28, \[pc, #36\] ; 00000094 +0000006c eddffa08 vldr s31, \[pc, #32\] ; 00000094 +00000070 ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 +00000074 ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 +00000078 ed9fea06 vldr s28, \[pc, #24\] ; 00000098 +0000007c eddffa05 vldr s31, \[pc, #20\] ; 00000098 +00000080 ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c +00000084 ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c +00000088 ed9fea03 vldr s28, \[pc, #12\] ; 0000009c +0000008c eddffa02 vldr s31, \[pc, #8\] ; 0000009c +00000090 00000000 .word 0x00000000 +00000094 00ff0000 .word 0x00ff0000 +00000098 ff00ffff .word 0xff00ffff +0000009c 00fff000 .word 0x00fff000 +000000a0 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 +000000a4 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 +000000a8 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 +000000ac 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 +000000b0 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 +000000b4 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 +000000b8 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 +000000bc 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 +000000c0 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 +000000c4 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 +000000c8 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 +000000cc 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 +000000d0 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec +000000d4 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec +000000d8 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec +000000dc 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec +000000e0 00000000 .word 0x00000000 +000000e4 0000ff00 .word 0x0000ff00 +000000e8 ffff00ff .word 0xffff00ff +000000ec 000fff00 .word 0x000fff00 +000000f0 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 +000000f4 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 +000000f8 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 +000000fc 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 +00000100 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 +00000104 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 +00000108 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 +0000010c 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 +00000110 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 +00000114 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 +00000118 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 +0000011c 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 +00000120 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c +00000124 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c +00000128 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c +0000012c 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c +00000130 00000000 .word 0x00000000 +00000134 000000ff .word 0x000000ff +00000138 ffffff00 .word 0xffffff00 +0000013c 0000fff0 .word 0x0000fff0 +00000140 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000144 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000148 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000014c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000150 ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 +00000154 ed9feb09 vldr d14, \[pc, #36\] ; 00000180 +00000158 eddfcb08 vldr d28, \[pc, #32\] ; 00000180 +0000015c eddffb07 vldr d31, \[pc, #28\] ; 00000180 +00000160 f3870e3f vmov.i64 d0, #0xffffffffffffffff +00000164 f387ee3f vmov.i64 d14, #0xffffffffffffffff +00000168 f3c7ce3f vmov.i64 d28, #0xffffffffffffffff +0000016c f3c7fe3f vmov.i64 d31, #0xffffffffffffffff +00000170 ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 +00000174 ed9feb03 vldr d14, \[pc, #12\] ; 00000188 +00000178 eddfcb02 vldr d28, \[pc, #8\] ; 00000188 +0000017c eddffb01 vldr d31, \[pc, #4\] ; 00000188 +00000180 00000000 .word 0x00000000 +00000184 ca000000 .word 0xca000000 +00000188 00000000 .word 0x00000000 +0000018c 0fff0000 .word 0x0fff0000 +00000190 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000194 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000198 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000019c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +000001a0 f2800e34 vmov.i64 d0, #0x0000000000ff0000 +000001a4 f280ee34 vmov.i64 d14, #0x0000000000ff0000 +000001a8 f2c0ce34 vmov.i64 d28, #0x0000000000ff0000 +000001ac f2c0fe34 vmov.i64 d31, #0x0000000000ff0000 +000001b0 f2800e39 vmov.i64 d0, #0x00000000ff0000ff +000001b4 f280ee39 vmov.i64 d14, #0x00000000ff0000ff +000001b8 f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff +000001bc f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff +000001c0 ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 +000001c4 ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 +000001c8 eddfcb00 vldr d28, \[pc\] ; 000001d0 +000001cc ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 +000001d0 00000000 .word 0x00000000 +000001d4 00fff000 .word 0x00fff000 +000001d8 f2800e30 vmov.i64 d0, #0x0000000000000000 +000001dc f280ee30 vmov.i64 d14, #0x0000000000000000 +000001e0 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +000001e4 f2c0fe30 vmov.i64 d31, #0x0000000000000000 +000001e8 f2800e32 vmov.i64 d0, #0x000000000000ff00 +000001ec f280ee32 vmov.i64 d14, #0x000000000000ff00 +000001f0 f2c0ce32 vmov.i64 d28, #0x000000000000ff00 +000001f4 f2c0fe32 vmov.i64 d31, #0x000000000000ff00 +000001f8 f2800e3d vmov.i64 d0, #0x00000000ffff00ff +000001fc f280ee3d vmov.i64 d14, #0x00000000ffff00ff +00000200 f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff +00000204 f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff +00000208 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 +0000020c 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 +00000210 0ddfcb00 vldreq d28, \[pc\] ; 00000218 +00000214 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 +00000218 00000000 .word 0x00000000 +0000021c 000fff00 .word 0x000fff00 +00000220 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000224 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000228 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000022c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000230 f2800e31 vmov.i64 d0, #0x00000000000000ff +00000234 f280ee31 vmov.i64 d14, #0x00000000000000ff +00000238 f2c0ce31 vmov.i64 d28, #0x00000000000000ff +0000023c f2c0fe31 vmov.i64 d31, #0x00000000000000ff +00000240 f2800e3e vmov.i64 d0, #0x00000000ffffff00 +00000244 f280ee3e vmov.i64 d14, #0x00000000ffffff00 +00000248 f2c0ce3e vmov.i64 d28, #0x00000000ffffff00 +0000024c f2c0fe3e vmov.i64 d31, #0x00000000ffffff00 +00000250 f2800e33 vmov.i64 d0, #0x000000000000ffff +00000254 f280ee33 vmov.i64 d14, #0x000000000000ffff +00000258 f2c0ce33 vmov.i64 d28, #0x000000000000ffff +0000025c f2c0fe33 vmov.i64 d31, #0x000000000000ffff +00000260 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000264 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000268 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000026c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000270 f3800e30 vmov.i64 d0, #0xff00000000000000 +00000274 f380ee30 vmov.i64 d14, #0xff00000000000000 +00000278 f3c0ce30 vmov.i64 d28, #0xff00000000000000 +0000027c f3c0fe30 vmov.i64 d31, #0xff00000000000000 +00000280 f3870e3f vmov.i64 d0, #0xffffffffffffffff +00000284 f387ee3f vmov.i64 d14, #0xffffffffffffffff +00000288 f3c7ce3f vmov.i64 d28, #0xffffffffffffffff +0000028c f3c7fe3f vmov.i64 d31, #0xffffffffffffffff +00000290 ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 +00000294 ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 +00000298 eddfcb00 vldr d28, \[pc\] ; 000002a0 +0000029c ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 +000002a0 0fff0000 .word 0x0fff0000 +000002a4 00000000 .word 0x00000000 +000002a8 f2800e30 vmov.i64 d0, #0x0000000000000000 +000002ac f280ee30 vmov.i64 d14, #0x0000000000000000 +000002b0 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +000002b4 f2c0fe30 vmov.i64 d31, #0x0000000000000000 +000002b8 ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 +000002bc ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 +000002c0 eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 +000002c4 eddffb07 vldr d31, \[pc, #28\] ; 000002e8 +000002c8 ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 +000002cc ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 +000002d0 eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 +000002d4 eddffb05 vldr d31, \[pc, #20\] ; 000002f0 +000002d8 ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 +000002dc ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 +000002e0 eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 +000002e4 eddffb03 vldr d31, \[pc, #12\] ; 000002f8 +000002e8 000ff000 .word 0x000ff000 +000002ec 00000000 .word 0x00000000 +000002f0 0ff00fff .word 0x0ff00fff +000002f4 f0000000 .word 0xf0000000 +000002f8 000fff00 .word 0x000fff00 +000002fc 00000000 .word 0x00000000 +00000300 f2800e30 vmov.i64 d0, #0x0000000000000000 +00000304 f280ee30 vmov.i64 d14, #0x0000000000000000 +00000308 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +0000030c f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000310 f2820e30 vmov.i64 d0, #0x0000ff0000000000 +00000314 f282ee30 vmov.i64 d14, #0x0000ff0000000000 +00000318 f2c2ce30 vmov.i64 d28, #0x0000ff0000000000 +0000031c f2c2fe30 vmov.i64 d31, #0x0000ff0000000000 +00000320 f3850e30 vmov.i64 d0, #0xffff00ff00000000 +00000324 f385ee30 vmov.i64 d14, #0xffff00ff00000000 +00000328 f3c5ce30 vmov.i64 d28, #0xffff00ff00000000 +0000032c f3c5fe30 vmov.i64 d31, #0xffff00ff00000000 +00000330 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 +00000334 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 +00000338 0ddfcb00 vldreq d28, \[pc\] ; 00000340 +0000033c 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 +00000340 000fff00 .word 0x000fff00 +00000344 00000000 .word 0x00000000 +00000348 f2800e30 vmov.i64 d0, #0x0000000000000000 +0000034c f280ee30 vmov.i64 d14, #0x0000000000000000 +00000350 f2c0ce30 vmov.i64 d28, #0x0000000000000000 +00000354 f2c0fe30 vmov.i64 d31, #0x0000000000000000 +00000358 f2810e30 vmov.i64 d0, #0x000000ff00000000 +0000035c f281ee30 vmov.i64 d14, #0x000000ff00000000 +00000360 f2c1ce30 vmov.i64 d28, #0x000000ff00000000 +00000364 f2c1fe30 vmov.i64 d31, #0x000000ff00000000 +00000368 f3860e30 vmov.i64 d0, #0xffffff0000000000 +0000036c f386ee30 vmov.i64 d14, #0xffffff0000000000 +00000370 f3c6ce30 vmov.i64 d28, #0xffffff0000000000 +00000374 f3c6fe30 vmov.i64 d31, #0xffffff0000000000 +00000378 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 +0000037c 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 +00000380 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 +00000384 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 +00000388 0000fff0 .word 0x0000fff0 +0000038c 00000000 .word 0x00000000 +00000390 ed9f1b00 vldr d1, \[pc\] ; 00000398 +00000394 00000000 andeq r0, r0, r0 +00000398 0000fff0 .word 0x0000fff0 +0000039c 00000000 .word 0x00000000 +000003a0 e2810000 add r0, r1, #0 +000003a4 ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 +000003a8 0000fff0 .word 0x0000fff0 +000003ac 00000000 .word 0x00000000 +000003b0 ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 +000003b4 ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 +000003b8 ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 +000003bc ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 +000003c0 ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 +000003c4 ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 +000003c8 ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 +000003cc ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 +000003d0 ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 +000003d4 ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 +000003d8 ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 +000003dc ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 +000003e0 eddf6a15 vldr s13, \[pc, #84\] ; 0000043c +000003e4 ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 +000003e8 eddf7a02 vldr s15, \[pc, #8\] ; 000003f8 +000003ec eddf0b13 vldr d16, \[pc, #76\] ; 00000440 +000003f0 eddf1b14 vldr d17, \[pc, #80\] ; 00000448 +000003f4 00000000 andeq r0, r0, r0 +000003f8 0000fff0 .word 0x0000fff0 +000003fc 00000000 .word 0x00000000 +00000400 ff000000 .word 0xff000000 +00000404 ff000001 .word 0xff000001 +00000408 0000fff0 .word 0x0000fff0 +0000040c 00000001 .word 0x00000001 +00000410 0000fff0 .word 0x0000fff0 +00000414 00000002 .word 0x00000002 +00000418 0000fff0 .word 0x0000fff0 +0000041c 00000003 .word 0x00000003 +00000420 ff000002 .word 0xff000002 +00000424 ff000003 .word 0xff000003 +00000428 0000fff0 .word 0x0000fff0 +0000042c 00000004 .word 0x00000004 +00000430 0000fff0 .word 0x0000fff0 +00000434 00000005 .word 0x00000005 +00000438 ff000004 .word 0xff000004 +0000043c ff000005 .word 0xff000005 +00000440 ff000005 .word 0xff000005 +00000444 ff000004 .word 0xff000004 +00000448 ff000004 .word 0xff000004 +0000044c 0000fff0 .word 0x0000fff0 -- 2.7.4