From 82a31ab5c11ee4595c2708615689883676d07d09 Mon Sep 17 00:00:00 2001 From: Yun Cai Date: Fri, 23 Jun 2017 17:49:43 +0800 Subject: [PATCH] clk: add saradc clk for gxl PD#146222: add saradc clk for gxl Change-Id: I5c82dfc4bc44908c10d96056b0d7a0cf3a64c46e Signed-off-by: Yun Cai --- drivers/amlogic/clk/gxl/clk_misc.c | 67 ++++++++++++++++++++++++++++ include/dt-bindings/clock/amlogic,gxl-clkc.h | 6 ++- 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/clk/gxl/clk_misc.c b/drivers/amlogic/clk/gxl/clk_misc.c index eb76f8de..c6659f3 100644 --- a/drivers/amlogic/clk/gxl/clk_misc.c +++ b/drivers/amlogic/clk/gxl/clk_misc.c @@ -323,6 +323,55 @@ static struct clk_gate pcm_sclk_gate = { }, }; +/* cts_sar_adc_clk */ +const char *saradc_parent_names[] = { "xtal", "clk81" }; +static struct clk_mux gxl_saradc_mux = { + .reg = (void *)HHI_SAR_CLK_CNTL, + .mask = 0x3, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "gxl_saradc_mux", + .ops = &clk_mux_ops, + .parent_names = saradc_parent_names, + .num_parents = 2, + .flags = (CLK_GET_RATE_NOCACHE), + }, +}; + +static struct clk_divider gxl_saradc_div = { + .reg = (void *)HHI_SAR_CLK_CNTL, + .shift = 0, + .width = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "gxl_saradc_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "gxl_saradc_mux" }, + .num_parents = 1, + .flags = (CLK_DIVIDER_ROUND_CLOSEST), + }, +}; + +static struct clk_gate gxl_saradc_gate = { + .reg = (void *)HHI_SAR_CLK_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "gxl_saradc_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "gxl_saradc_div" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_hw *saradc_hws[] = { +[CLKID_SARADC_MUX - CLKID_SARADC_MUX] = &gxl_saradc_mux.hw, +[CLKID_SARADC_DIV - CLKID_SARADC_MUX] = &gxl_saradc_div.hw, +[CLKID_SARADC_GATE - CLKID_SARADC_MUX] = &gxl_saradc_gate.hw, +}; + void amlogic_init_misc(void) { /* cts_vdin_meas_clk */ @@ -357,6 +406,11 @@ void amlogic_init_misc(void) pcm_sclk_div.reg = clk_base + (u64)(pcm_sclk_div.reg); pcm_sclk_gate.reg = clk_base + (u64)(pcm_sclk_gate.reg); + /* cts_sar_adc_clk */ + gxl_saradc_mux.reg = clk_base + (u64)(gxl_saradc_mux.reg); + gxl_saradc_div.reg = clk_base + (u64)(gxl_saradc_div.reg); + gxl_saradc_gate.reg = clk_base + (u64)(gxl_saradc_gate.reg); + clks[CLKID_VDIN_MEAS_COMP] = clk_register_composite(NULL, "vdin_meas_composite", meas_parent_names, 6, @@ -422,6 +476,19 @@ void amlogic_init_misc(void) pr_err("%s: %d clk_register_composite pcm_mclk_composite error\n", __func__, __LINE__); + clks[CLKID_SARADC_COMP] = clk_register_composite(NULL, + "saradc_composite", + saradc_parent_names, 2, + saradc_hws[CLKID_SARADC_MUX - CLKID_SARADC_MUX], + &clk_mux_ops, + saradc_hws[CLKID_SARADC_DIV - CLKID_SARADC_MUX], + &clk_divider_ops, + saradc_hws[CLKID_SARADC_GATE - CLKID_SARADC_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_PDM_COMP])) + pr_err("%s: %d clk_register_composite saradc_composite error\n", + __func__, __LINE__); + clks[CLKID_PCM_SCLK_DIV] = clk_register(NULL, &pcm_sclk_div.hw); WARN_ON(IS_ERR(clks[CLKID_PCM_SCLK_DIV])); diff --git a/include/dt-bindings/clock/amlogic,gxl-clkc.h b/include/dt-bindings/clock/amlogic,gxl-clkc.h index d0904a2..9b4079c 100644 --- a/include/dt-bindings/clock/amlogic,gxl-clkc.h +++ b/include/dt-bindings/clock/amlogic,gxl-clkc.h @@ -262,7 +262,11 @@ #define CLKID_PCM_SCLK_DIV (CLKID_MISC_BASE + 20) #define CLKID_PCM_SCLK_GATE (CLKID_MISC_BASE + 21) #define CLKID_I958_COMP_SPDIF (CLKID_MISC_BASE + 22) +#define CLKID_SARADC_MUX (CLKID_MISC_BASE + 23) +#define CLKID_SARADC_DIV (CLKID_MISC_BASE + 24) +#define CLKID_SARADC_GATE (CLKID_MISC_BASE + 25) +#define CLKID_SARADC_COMP (CLKID_MISC_BASE + 26) -#define NR_CLKS (OTHER_BASE + 102) +#define NR_CLKS (OTHER_BASE + 106) #endif /* __GX_CLKC_H */ -- 2.7.4