From 82a2501c93a16ee3a601da369159063ac2f303d7 Mon Sep 17 00:00:00 2001 From: Zongdong Jiao Date: Sat, 27 Jul 2019 17:58:38 +0800 Subject: [PATCH] hdmitx: update phy parameters [2/2] PD#OTT-5448 Problem: need update phy parameters Solution: regress raven parameters to trunk Verify: g12/u212 Change-Id: I84149dd900b584c209dd052e22b6dc60162e6c16 Signed-off-by: Zongdong Jiao --- .../media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 130 +++++++++++++-------- .../linux/amlogic/media/vout/hdmi_tx/hdmi_common.h | 10 ++ 2 files changed, 93 insertions(+), 47 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 14385cc..94c0a73 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1875,23 +1875,38 @@ static void set_phy_by_mode(unsigned int mode) case MESON_CPU_ID_G12A: case MESON_CPU_ID_G12B: switch (mode) { - case 1: /* 5.94/4.5/3.7Gbps */ + case HDMI_PHYPARA_6G: /* 5.94Gbps */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb76d4); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); + break; + case HDMI_PHYPARA_4p5G: /* 4.5Gbps*/ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65d4); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); + break; + case HDMI_PHYPARA_3p7G: /* 3.7Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4); if (hdev->dongle_mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); break; - case 2: /* 2.97Gbps */ + case HDMI_PHYPARA_3G: /* 2.97Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6272); if (hdev->dongle_mode) hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); break; - case 3: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_270M: /* SD format, 480p/576p, 270Mbps */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb5252); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); + break; + case HDMI_PHYPARA_DEF: /* less than 2.97G */ default: - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242); + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); break; @@ -1899,17 +1914,20 @@ static void set_phy_by_mode(unsigned int mode) break; case MESON_CPU_ID_SM1: switch (mode) { - case 1: /* 5.94/4.5/3.7Gbps */ + case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */ + case HDMI_PHYPARA_4p5G: + case HDMI_PHYPARA_3p7G: hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); break; - case 2: /* 2.97Gbps */ + case HDMI_PHYPARA_3G: /* 2.97Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb42a2); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); break; - case 3: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_DEF: default: hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); @@ -1919,17 +1937,20 @@ static void set_phy_by_mode(unsigned int mode) break; case MESON_CPU_ID_TM2: switch (mode) { - case 1: /* 5.94/4.5/3.7Gbps */ + case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */ + case HDMI_PHYPARA_4p5G: + case HDMI_PHYPARA_3p7G: hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33EB65c4); hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x0000080b); break; - case 2: /* 2.97Gbps */ + case HDMI_PHYPARA_3G: /* 2.97Gbps */ hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb42a5); hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003); break; - case 3: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_DEF: default: hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb4262); hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); @@ -1942,15 +1963,18 @@ static void set_phy_by_mode(unsigned int mode) case MESON_CPU_ID_GXTVBB: /* other than GXL */ switch (mode) { - case 1: /* 5.94Gbps, 3.7125Gbsp */ + case HDMI_PHYPARA_6G: /* 5.94Gbps, 3.7125Gbsp */ + case HDMI_PHYPARA_4p5G: + case HDMI_PHYPARA_3p7G: hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33353245); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2100115b); break; - case 2: /* 2.97Gbps */ + case HDMI_PHYPARA_3G: /* 2.97Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33634283); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0xb000115b); break; - case 3: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_DEF: default: hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33632122); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2000115b); @@ -1966,18 +1990,21 @@ static void set_phy_by_mode(unsigned int mode) case MESON_CPU_ID_TXHD: default: switch (mode) { - case 1: /* 5.94Gbps, 3.7125Gbsp */ + case HDMI_PHYPARA_6G: /* 5.94Gbps, 3.7125Gbsp */ + case HDMI_PHYPARA_4p5G: + case HDMI_PHYPARA_3p7G: hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x333d3282); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2136315b); break; - case 2: /* 2.97Gbps */ + case HDMI_PHYPARA_3G: /* 2.97Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33303382); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2036315b); break; - case 3: /* 1.485Gbps */ + case HDMI_PHYPARA_DEF: /* 1.485Gbps */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33303042); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2016315b); break; + case HDMI_PHYPARA_270M: default: /* 742.5Mbps, and below */ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33604132); hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x0016315b); @@ -1991,8 +2018,8 @@ static void hdmitx_set_phy(struct hdmitx_dev *hdev) { if (!hdev) return; + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0); if (hdev->chip_type == MESON_CPU_ID_TM2) { - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0); /* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */ #define RESET_HDMI_PHY() \ @@ -2007,14 +2034,13 @@ do { \ hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x1, 17, 1); hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x0, 17, 1); hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4); - msleep(100); + msleep(20); RESET_HDMI_PHY(); RESET_HDMI_PHY(); RESET_HDMI_PHY(); #undef RESET_HDMI_PHY } else { - hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0); /* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */ #define RESET_HDMI_PHY() \ do { \ @@ -2029,7 +2055,7 @@ do { \ if (hdev->chip_type >= MESON_CPU_ID_GXL) hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 17, 1); hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4); - msleep(100); + msleep(20); RESET_HDMI_PHY(); RESET_HDMI_PHY(); RESET_HDMI_PHY(); @@ -2037,48 +2063,58 @@ do { \ } switch (hdev->cur_VIC) { - case HDMI_4k2k_24: - case HDMI_4k2k_25: - case HDMI_4k2k_30: - case HDMI_4k2k_smpte_24: - case HDMI_4096x2160p25_256x135: - case HDMI_4096x2160p30_256x135: - if ((hdev->para->cs == COLORSPACE_YUV422) - || (hdev->para->cd == COLORDEPTH_24B)) - set_phy_by_mode(2); - else - set_phy_by_mode(1); - break; case HDMI_3840x2160p50_16x9: case HDMI_3840x2160p60_16x9: case HDMI_4096x2160p50_256x135: case HDMI_4096x2160p60_256x135: - if (hdev->para->cs == COLORSPACE_YUV420) - set_phy_by_mode(2); + if (hdev->para->cs != COLORSPACE_YUV420) + set_phy_by_mode(HDMI_PHYPARA_6G); else - set_phy_by_mode(1); + if (hdev->para->cd == COLORDEPTH_36B) + set_phy_by_mode(HDMI_PHYPARA_4p5G); + else if (hdev->para->cd == COLORDEPTH_30B) + set_phy_by_mode(HDMI_PHYPARA_3p7G); + else + set_phy_by_mode(HDMI_PHYPARA_3G); break; case HDMI_3840x2160p50_16x9_Y420: case HDMI_3840x2160p60_16x9_Y420: case HDMI_4096x2160p50_256x135_Y420: case HDMI_4096x2160p60_256x135_Y420: - if (hdev->para->cd == COLORDEPTH_24B) - set_phy_by_mode(2); + if (hdev->para->cd == COLORDEPTH_36B) + set_phy_by_mode(HDMI_PHYPARA_4p5G); + else if (hdev->para->cd == COLORDEPTH_30B) + set_phy_by_mode(HDMI_PHYPARA_3p7G); else - set_phy_by_mode(1); + set_phy_by_mode(HDMI_PHYPARA_3G); break; - case HDMI_1080p60: - case HDMI_1080p50: - if (hdev->flag_3dfp) - set_phy_by_mode(2); + case HDMI_4k2k_24: + case HDMI_4k2k_25: + case HDMI_4k2k_30: + case HDMI_4k2k_smpte_24: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + if ((hdev->para->cs == COLORSPACE_YUV422) + || (hdev->para->cd == COLORDEPTH_24B)) + set_phy_by_mode(HDMI_PHYPARA_3G); else - set_phy_by_mode(3); + if (hdev->para->cd == COLORDEPTH_36B) + set_phy_by_mode(HDMI_PHYPARA_4p5G); + else if (hdev->para->cd == COLORDEPTH_30B) + set_phy_by_mode(HDMI_PHYPARA_3p7G); + else + set_phy_by_mode(HDMI_PHYPARA_3G); break; + case HDMI_720x480p60_16x9: + case HDMI_720x576p50_16x9: + case HDMI_720x480i60_16x9: + case HDMI_720x576i50_16x9: + set_phy_by_mode(HDMI_PHYPARA_270M); + break; + case HDMI_1080p60: + case HDMI_1080p50: default: - if (hdev->flag_3dfp) - set_phy_by_mode(3); - else - set_phy_by_mode(4); + set_phy_by_mode(HDMI_PHYPARA_DEF); break; } } diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h index e640616..bc85483 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h @@ -251,6 +251,16 @@ enum hdmi_vic { #define HDMI_4k2k_smpte_50_y420 HDMI_4096x2160p50_256x135_Y420 #define HDMI_4k2k_smpte_60_y420 HDMI_4096x2160p60_256x135_Y420 +enum hdmi_phy_para { + HDMI_PHYPARA_6G = 1, /* 2160p60hz 444 8bit */ + HDMI_PHYPARA_4p5G, /* 2160p50hz 420 12bit */ + HDMI_PHYPARA_3p7G, /* 2160p30hz 444 10bit */ + HDMI_PHYPARA_3G, /* 2160p24hz 444 8bit */ + HDMI_PHYPARA_LT3G, /* 1080p60hz 444 12bit */ + HDMI_PHYPARA_DEF = HDMI_PHYPARA_LT3G, + HDMI_PHYPARA_270M, /* 480p60hz 444 8bit */ +}; + enum hdmi_audio_fs; struct dtd; -- 2.7.4