From 828c4a1c7099905e2449692ee32fc64b4a35b507 Mon Sep 17 00:00:00 2001 From: Pat Gavlin Date: Fri, 12 Aug 2016 16:34:18 -0700 Subject: [PATCH] Massage the code a bit for jit-format w/ Clang 3.8. Manually insert a few braces that would otherwise have been inserted in the wrong place. --- src/jit/codegencommon.cpp | 4 +--- src/jit/codegenlegacy.cpp | 5 ++--- src/jit/compiler.cpp | 6 ++++++ src/jit/emit.cpp | 12 ++++++++---- src/jit/emit.h | 12 +++++++----- src/jit/emitxarch.cpp | 14 ++++++++++++++ src/jit/gentree.cpp | 26 ++++++++++++++++++++++++-- src/jit/jiteh.cpp | 11 +++++++++-- src/jit/lclvars.cpp | 2 +- src/jit/lsra.cpp | 6 ++++-- src/jit/optcse.cpp | 3 --- src/jit/regalloc.cpp | 1 + 12 files changed, 77 insertions(+), 25 deletions(-) diff --git a/src/jit/codegencommon.cpp b/src/jit/codegencommon.cpp index e3b95a3..611171d 100755 --- a/src/jit/codegencommon.cpp +++ b/src/jit/codegencommon.cpp @@ -1804,6 +1804,7 @@ bool CodeGen::genCreateAddrMode(GenTreePtr addr, #ifndef LEGACY_BACKEND assert(nogen == true); #endif // !LEGACY_BACKEND + /* The following indirections are valid address modes on x86/x64: @@ -11666,10 +11667,7 @@ void CodeGen::genIPmappingGen() compiler->eeSetLIdone(); } -/*****************************************************************************/ #endif // DEBUGGING_SUPPORT -/*****************************************************************************/ - /*============================================================================ * diff --git a/src/jit/codegenlegacy.cpp b/src/jit/codegenlegacy.cpp index b6a9502..7109547 100644 --- a/src/jit/codegenlegacy.cpp +++ b/src/jit/codegenlegacy.cpp @@ -10891,7 +10891,8 @@ REG_OK: switch (dstType) { - case TYP_INT: // conv.ovf.i8.i4 + case TYP_INT: + // conv.ovf.i8.i4 /* Generate the following sequence test loDWord, loDWord // set flags @@ -21297,9 +21298,7 @@ void CodeGen::genSetScopeInfo (unsigned which, compiler->eeSetLVinfo(which, startOffs, length, ilVarNum, LVnum, name, avail, varLoc); } -/*****************************************************************************/ #endif // DEBUGGING_SUPPORT -/*****************************************************************************/ /***************************************************************************** * diff --git a/src/jit/compiler.cpp b/src/jit/compiler.cpp index a79ddb3..b837cf5 100644 --- a/src/jit/compiler.cpp +++ b/src/jit/compiler.cpp @@ -5014,13 +5014,19 @@ void Compiler::compCompileFinish() if (rpFrameType == FT_EBP_FRAME) printf("%3s | ", STR_FPBASE); else if (rpFrameType == FT_ESP_FRAME) + { printf("%3s | ", STR_SPBASE ); + } #if DOUBLE_ALIGN else if (rpFrameType == FT_DOUBLE_ALIGN_FRAME) + { printf("dbl | "); + } #endif else // (rpFrameType == FT_NOT_SET) + { printf("??? | "); + } if (fgHasLoops) printf("LOOP |"); diff --git a/src/jit/emit.cpp b/src/jit/emit.cpp index 6111a2b..5eb5379 100644 --- a/src/jit/emit.cpp +++ b/src/jit/emit.cpp @@ -3170,8 +3170,8 @@ const char * emitter::emitFncName(CORINFO_METHOD_HANDLE methHnd) return emitComp->eeGetMethodFullName(methHnd); } -/*****************************************************************************/ #endif//DEBUG + /***************************************************************************** * * Be very careful, some instruction descriptors are allocated as "tiny" and @@ -3937,7 +3937,9 @@ AGAIN: */ srcInstrOffs = jmpIG->igOffs + jmp->idjOffs; - dstOffs = tgtIG->igOffs; /* Note that the destination is always the beginning of an IG, so no need for an offset inside it */ + + /* Note that the destination is always the beginning of an IG, so no need for an offset inside it */ + dstOffs = tgtIG->igOffs; #if defined(_TARGET_ARM_) srcEncodingOffs = srcInstrOffs + 4; // For relative branches, ARM PC is always considered to be the instruction address + 4 @@ -4146,9 +4148,11 @@ AGAIN: #if defined(_TARGET_XARCH_) jmp->idCodeSize(jsz); #elif defined(_TARGET_ARM_) +#if 0 // This is done as part of emitSetShortJump(): - // insSize isz = emitInsSize(jmp->idInsFmt()); - // jmp->idInsSize(isz); + insSize isz = emitInsSize(jmp->idInsFmt()); + jmp->idInsSize(isz); +#endif #elif defined(_TARGET_ARM64_) // The size of IF_LARGEJMP/IF_LARGEADR/IF_LARGELDC are 8 or 12. // All other code size is 4. diff --git a/src/jit/emit.h b/src/jit/emit.h index aaf042e..52cb3b4 100644 --- a/src/jit/emit.h +++ b/src/jit/emit.h @@ -597,11 +597,14 @@ protected: { private: #if defined(_TARGET_XARCH_) && !defined(LEGACY_BACKEND) - instruction _idIns :9; // The assembly instruction + // The assembly instruction + instruction _idIns :9; #else // !defined(_TARGET_XARCH_) || defined(LEGACY_BACKEND) - instruction _idIns :8; // The assembly instruction + // The assembly instruction + instruction _idIns :8; #endif // !defined(_TARGET_XARCH_) || defined(LEGACY_BACKEND) - insFormat _idInsFmt :8; // The format for the instruction + // The format for the instruction + insFormat _idInsFmt :8; public: instruction idIns() const { return _idIns; } @@ -649,8 +652,7 @@ protected: // At this point we have fully consumed first DWORD so that next field // doesn't cross a byte boundary. #elif defined(_TARGET_ARM64_) - // Moved the definition of '_idOpSize' later - // so that we don't cross a 32-bit boundary when laying out bitfields +// Moved the definition of '_idOpSize' later so that we don't cross a 32-bit boundary when laying out bitfields #else // ARM or x86-LEGACY_BACKEND opSize _idOpSize :2; // operand size: 0=1 , 1=2 , 2=4 , 3=8 #endif // ARM or x86-LEGACY_BACKEND diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp index 2687b49..327b044 100644 --- a/src/jit/emitxarch.cpp +++ b/src/jit/emitxarch.cpp @@ -7030,10 +7030,14 @@ PRINT_CONSTANT: printf(", "); #ifdef RELOC_SUPPORT if (cnsVal.cnsReloc) + { emitDispReloc(val); + } else #endif + { goto PRINT_CONSTANT; + } } break; @@ -7249,10 +7253,14 @@ PRINT_CONSTANT: printf(", "); #ifdef RELOC_SUPPORT if (id->idIsCnsReloc()) + { emitDispReloc(val); + } else #endif + { goto PRINT_CONSTANT; + } break; case IF_RRD: @@ -7272,7 +7280,9 @@ PRINT_CONSTANT: case IF_RRW_MRD: if (ins == INS_movsx || ins == INS_movzx) + { attr = EA_PTRSIZE; + } #ifdef _TARGET_AMD64_ else if (ins == INS_movsxd) { @@ -7376,10 +7386,14 @@ PRINT_CONSTANT: val = emitGetInsSC(id); #ifdef RELOC_SUPPORT if (id->idIsCnsReloc()) + { emitDispReloc(val); + } else #endif + { goto PRINT_CONSTANT; + } break; #if FEATURE_STACK_FP_X87 diff --git a/src/jit/gentree.cpp b/src/jit/gentree.cpp index 6b2c18e..7677f74 100644 --- a/src/jit/gentree.cpp +++ b/src/jit/gentree.cpp @@ -8419,12 +8419,18 @@ Compiler::gtDispNodeName(GenTree *tree) gtfType = " nullcheck"; if (tree->gtFlags & GTF_CALL_VIRT_VTABLE) + { gtfType = " ind"; + } else if (tree->gtFlags & GTF_CALL_VIRT_STUB) + { gtfType = " stub"; + } #ifdef FEATURE_READYTORUN_COMPILER else if (tree->gtCall.IsR2RRelativeIndir()) + { gtfType = " r2r_ind"; + } #endif // FEATURE_READYTORUN_COMPILER else if (tree->gtFlags & GTF_CALL_UNMANAGED) { @@ -8994,26 +9000,40 @@ void Compiler::gtGetLclVarNameInfo(unsigned lclNum, const char** else if (lclNum == lvaInlinedPInvokeFrameVar) ilName = "PInvokeFrame"; else if (lclNum == lvaGSSecurityCookie) + { ilName = "GsCookie"; + } #if FEATURE_FIXED_OUT_ARGS else if (lclNum == lvaPInvokeFrameRegSaveVar) + { ilName = "PInvokeFrameRegSave"; + } else if (lclNum == lvaOutgoingArgSpaceVar) + { ilName = "OutArgs"; + } #endif // FEATURE_FIXED_OUT_ARGS #ifdef _TARGET_ARM_ else if (lclNum == lvaPromotedStructAssemblyScratchVar) + { ilName = "PromotedStructScratch"; + } #endif // _TARGET_ARM_ #if !FEATURE_EH_FUNCLETS else if (lclNum == lvaShadowSPslotsVar) + { ilName = "EHSlots"; + } #endif // !FEATURE_EH_FUNCLETS else if (lclNum == lvaLocAllocSPvar) + { ilName = "LocAllocSP"; + } #if FEATURE_EH_FUNCLETS else if (lclNum == lvaPSPSym) + { ilName = "PSPSym"; + } #endif // FEATURE_EH_FUNCLETS else { @@ -14737,7 +14757,7 @@ void GenTree::LabelIndex(Compiler* comp, bool isConst) break; } else if (gtOp.gtOp1->OperGet() == GT_CNS_INT) - { + { gtOp.gtOp2->LabelIndex(comp, isConst); break; } @@ -14749,8 +14769,10 @@ void GenTree::LabelIndex(Compiler* comp, bool isConst) } } +// Note that the value of the below field doesn't matter; it exists only to provide a distinguished address. +// // static -FieldSeqNode FieldSeqStore::s_notAField(NULL, NULL); // Value doesn't matter; exists only to provide a distinguished address. +FieldSeqNode FieldSeqStore::s_notAField(NULL, NULL); // FieldSeqStore methods. FieldSeqStore::FieldSeqStore(IAllocator* alloc) : m_alloc(alloc), m_canonMap(new (alloc) FieldSeqNodeCanonMap(alloc)) diff --git a/src/jit/jiteh.cpp b/src/jit/jiteh.cpp index 8098992..77441a9 100644 --- a/src/jit/jiteh.cpp +++ b/src/jit/jiteh.cpp @@ -802,11 +802,18 @@ unsigned Compiler::ehTrueEnclosingTryIndexIL(unsigned regionIndex) { regionIndex = HBtab->ebdEnclosingTryIndex; if (regionIndex == EHblkDsc::NO_ENCLOSING_INDEX) - break; // No enclosing 'try'; we're done + { + // No enclosing 'try'; we're done + break; + } HBtab = ehGetDsc(regionIndex); if (!EHblkDsc::ebdIsSameILTry(ehDscRoot, HBtab)) - break; // Found an enclosing 'try' that has a different 'try' region (is not mutually-protect with the original region). Return it. + { + // Found an enclosing 'try' that has a different 'try' region (is not mutually-protect with the + // original region). Return it. + break; + } } return regionIndex; diff --git a/src/jit/lclvars.cpp b/src/jit/lclvars.cpp index 918e7ae..053fee9 100644 --- a/src/jit/lclvars.cpp +++ b/src/jit/lclvars.cpp @@ -6542,8 +6542,8 @@ void Compiler::lvaStressLclFld() fgWalkAllTreesPre(lvaStressLclFldCB, &Args); } -/*****************************************************************************/ #endif // DEBUG + /***************************************************************************** * * A little routine that displays a local variable bitset. diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp index 1174593..e7e5404 100644 --- a/src/jit/lsra.cpp +++ b/src/jit/lsra.cpp @@ -668,8 +668,10 @@ LinearScan::applyCalleeSaveHeuristics(RefPosition* rp) } else #endif // DEBUG - // Set preferences so that this register set will be preferred for earlier refs - theInterval->updateRegisterPreferences(rp->registerAssignment); + { + // Set preferences so that this register set will be preferred for earlier refs + theInterval->updateRegisterPreferences(rp->registerAssignment); + } } void diff --git a/src/jit/optcse.cpp b/src/jit/optcse.cpp index 424939d..da969a7 100644 --- a/src/jit/optcse.cpp +++ b/src/jit/optcse.cpp @@ -2119,10 +2119,7 @@ void Compiler::optOptimizeValnumCSEs() optValnumCSE_phase = false; } -/*****************************************************************************/ #endif // FEATURE_VALNUM_CSE -/*****************************************************************************/ - /***************************************************************************** * diff --git a/src/jit/regalloc.cpp b/src/jit/regalloc.cpp index ec040d7..bebbac7 100644 --- a/src/jit/regalloc.cpp +++ b/src/jit/regalloc.cpp @@ -5269,6 +5269,7 @@ bool Compiler::rpMustCreateEBPFrame(INDEBUG( const char ** wbReason)) } #ifdef LEGACY_BACKEND // We don't use any of the old register allocator functions when LSRA is used instead. + /***************************************************************************** * * Predict which variables will be assigned to registers -- 2.7.4