From 824a88b5671fc88ef5dd0bf6861f7497b3db0d28 Mon Sep 17 00:00:00 2001 From: Khiem Nguyen Date: Fri, 18 Jan 2019 11:47:52 +0100 Subject: [PATCH] arm64: dts: r8a7796: Add cpuidle support for CA57 cores Enable cpuidle (core shutdown) support for R-Car M3-W CA57 cores. Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they help to keep the performance and reduce the power consumption. Signed-off-by: Khiem Nguyen Signed-off-by: Takeshi Kihara [dien.pham.ry: Apply new cpuidle parameters] Signed-off-by: Dien Pham Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/1547808474-19427-4-git-send-email-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 8c9bf98..6e6cf7d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -160,6 +160,7 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; @@ -174,6 +175,7 @@ power-domains = <&sysc R8A7796_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -243,6 +245,19 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; }; extal_clk: extal { -- 2.7.4