From 82296f20f935d5704bd9366c38e12522bc1cb918 Mon Sep 17 00:00:00 2001 From: Hyeongsik Min Date: Mon, 24 Oct 2016 07:28:20 +0900 Subject: [PATCH] Add support for ARM Cortex A17 microarchitecture Added the event list of the ARM Cortex A17 based on ARM DDI 0535C. Change-Id: Idb49683425dce267d26636dfc5ae69f1d8db6a7e Signed-off-by: Hyeongsik Min --- events/Makefile.am | 1 + events/Makefile.in | 1 + events/arm/armv7-ca17/events | 77 ++++++++++++++++++++++++++++++++ events/arm/armv7-ca17/unit_masks | 4 ++ libop/op_cpu_type.c | 3 ++ libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + utils/ophelp.c | 6 +++ 8 files changed, 94 insertions(+) create mode 100644 events/arm/armv7-ca17/events create mode 100644 events/arm/armv7-ca17/unit_masks diff --git a/events/Makefile.am b/events/Makefile.am index 56f9020..e138c02 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -49,6 +49,7 @@ event_files = \ arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ arm/armv7-ca15/events arm/armv7-ca15/unit_masks \ + arm/armv7-ca17/events arm/armv7-ca17/unit_masks \ arm/mpcore/events arm/mpcore/unit_masks \ arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \ arm/armv8-xgene/events arm/armv8-xgene/unit_masks \ diff --git a/events/Makefile.in b/events/Makefile.in index ac085e7..c8f6d5e 100644 --- a/events/Makefile.in +++ b/events/Makefile.in @@ -332,6 +332,7 @@ event_files = \ arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ arm/armv7-ca15/events arm/armv7-ca15/unit_masks \ + arm/armv7-ca17/events arm/armv7-ca17/unit_masks \ arm/mpcore/events arm/mpcore/unit_masks \ arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \ arm/armv8-xgene/events arm/armv8-xgene/unit_masks \ diff --git a/events/arm/armv7-ca17/events b/events/arm/armv7-ca17/events new file mode 100644 index 0000000..259852c --- /dev/null +++ b/events/arm/armv7-ca17/events @@ -0,0 +1,77 @@ +# ARM Cortex A17 events +# From Cortex A17 TRM +# +include:arm/armv7-common + +event:0x40 counters:1,2,3,4,5,6 um:zero minimum:500 name:L1D_CACHE_LD : Level 1 data cache access, read +event:0x41 counters:1,2,3,4,5,6 um:zero minimum:500 name:L1D_CACHE_ST : Level 1 data cache access, write + +event:0x50 counters:1,2,3,4,5,6 um:zero minimum:500 name:L2D_CACHE_LD : Level 2 data cache access, read +event:0x51 counters:1,2,3,4,5,6 um:zero minimum:500 name:L2D_CACHE_ST : Level 2 data cache access, write + +event:0x56 counters:1,2,3,4,5,6 um:zero minimum:500 name:L2D_CACHE_WB_VICTIM : Level 2 data cache write-back, victim +event:0x57 counters:1,2,3,4,5,6 um:zero minimum:500 name:L2D_CACHE_WB_CLEAN : Level 2 data cache write-back, cleaning and coherency +event:0x58 counters:1,2,3,4,5,6 um:zero minimum:500 name:L2D_CACHE_INVAL : Level 2 data cache invalidate + +event:0x62 counters:1,2,3,4,5,6 um:zero minimum:500 name:BUS_ACCESS_SHARED : Bus access, normal, cacheable, shareable +event:0x63 counters:1,2,3,4,5,6 um:zero minimum:500 name:BUS_ACCESS_NOT_SHARED : Bus access, not normal, cacheable, shareable +event:0x64 counters:1,2,3,4,5,6 um:zero minimum:500 name:BUS_ACCESS_NORMAL : Bus access, normal +event:0x65 counters:1,2,3,4,5,6 um:zero minimum:500 name:BUS_ACCESS_PERIPH : Bus access, peripheral +event:0x66 counters:1,2,3,4,5,6 um:zero minimum:500 name:MEM_ACCESS_LD : Data memory access, read +event:0x67 counters:1,2,3,4,5,6 um:zero minimum:500 name:MEM_ACCESS_ST : Data memory access, write +event:0x68 counters:1,2,3,4,5,6 um:zero minimum:500 name:UNALIGNED_LD_SPEC : Unaligned access, read +event:0x69 counters:1,2,3,4,5,6 um:zero minimum:500 name:UNALIGNED_ST_SPEC : Unaligned access, write +event:0x6A counters:1,2,3,4,5,6 um:zero minimum:500 name:UNALIGNED_LDST_SPEC : Unaligned access + +event:0x6C counters:1,2,3,4,5,6 um:zero minimum:500 name:LDREX_SPEC : ldrex instruction speculatively executed +event:0x6E counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_FAIL_SPEC : strex instruction speculatively executed, fail +event:0x6F counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_SPEC : strex instruction speculatively executed + +event:0x70 counters:1,2,3,4,5,6 um:zero minimum:500 name:LD_SPEC : Load instruction speculatively executed +event:0x71 counters:1,2,3,4,5,6 um:zero minimum:500 name:ST_SPEC : Store instruction speculatively executed +event:0x72 counters:1,2,3,4,5,6 um:zero minimum:500 name:LDST_SPEC : Load or store instruction speculatively executed +event:0x73 counters:1,2,3,4,5,6 um:zero minimum:500 name:DP_SPEC : Data processing instruction speculatively executed +event:0x74 counters:1,2,3,4,5,6 um:zero minimum:500 name:ASE_SPEC : Advanced SIMD extension instruction speculatively executed +event:0x75 counters:1,2,3,4,5,6 um:zero minimum:500 name:VFP_SPEC : Floating-point extension instruction speculatively executed +event:0x76 counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_WRITE_SPEC : Software change of the PC instruction speculatively executed + +event:0x78 counters:1,2,3,4,5,6 um:zero minimum:500 name:BR_IMMED_SPEC : Immediate branch instruction speculatively executed +event:0x79 counters:1,2,3,4,5,6 um:zero minimum:500 name:BR_RETURN_SPEC : Procedure return instruction speculatively executed +event:0x7A counters:1,2,3,4,5,6 um:zero minimum:500 name:BR_INDIRECT_SPEC : Indirect branch instruction speculatively executed + +event:0x7C counters:1,2,3,4,5,6 um:zero minimum:500 name:ISB_SPEC : ISB barrier instruction speculatively executed +event:0x7D counters:1,2,3,4,5,6 um:zero minimum:500 name:DSB_SPEC : DSB barrier instruction speculatively executed +event:0x7E counters:1,2,3,4,5,6 um:zero minimum:500 name:DMB_SPEC : DMB barrier instruction speculatively executed + +event:0x81 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_UNDEF : Exception taken, Undefined Instruction +event:0x8A counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_HVC : Exception taken, Hypervisor Call + +event:0xC0 counters:1,2,3,4,5,6 um:zero minimum:500 name:LF_STALL : Linefill caused an instruction side stall +event:0xC1 counters:1,2,3,4,5,6 um:zero minimum:500 name:PTW_STALL : Translation table walk caused an instruction side stall +event:0xC2 counters:1,2,3,4,5,6 um:zero minimum:500 name:I_TAG_RAM_RD : Number of set of 4 ways read in the instruction cache - Tag RAM +event:0xC3 counters:1,2,3,4,5,6 um:zero minimum:500 name:I_DATA_RAM_RD : Number of ways read in the instruction cache - Data RAM +event:0xC4 counters:1,2,3,4,5,6 um:zero minimum:500 name:I_BTAC_RAM_RD : Number of ways read in the instruction BTAC RAM + +event:0xCA counters:1,2,3,4,5,6 um:zero minimum:500 name:DATA_SNOOP : Data snooped from other processor + +event:0xD3 counters:1,2,3,4,5,6 um:zero minimum:500 name:D_LSU_SLOT_FULL : Duration during which all slots in the Load-Store Unit are busy +event:0xD8 counters:1,2,3,4,5,6 um:zero minimum:500 name:LS_IQ_FULL : Duration during which all slots in the Load-Store Issue queue are busy +event:0xD9 counters:1,2,3,4,5,6 um:zero minimum:500 name:DP_IQ_FULL : Duration during which all slots in the Data Processing issue queue are busy. +event:0xDA counters:1,2,3,4,5,6 um:zero minimum:500 name:DE_IQ_FULL : Duration during which all slots in the Data Engine issue queue are busy +event:0xDB counters:1,2,3,4,5,6 um:zero minimum:500 name:FLUSH_DE_NEON : Number of NEON instruction which fail their condition code and lead to a flush of the DE pipe +event:0xDC counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_TRAP_HYP : Number of Trap to hypervisor +event:0xDE counters:1,2,3,4,5,6 um:zero minimum:500 name:ETM_EXT_OUT0 : PTM EXTOUT 0 +event:0xDF counters:1,2,3,4,5,6 um:zero minimum:500 name:ETM_EXT_OUT1 : PTM EXTOUT 1 + +event:0xE0 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW : Duration during which the MMU handle a translation table walk. +event:0xE1 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW_ST1 : Duration during which the MMU handle a Stage1 translation table walk +event:0xE2 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW_ST2 : Duration during which the MMU handle a Stage2 translation table walk +event:0xE3 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW_LSU : Duration during which the MMU handle a translation table walk requested by the Load Store Unit +event:0xE4 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW_ISIDE : Duration during which the MMU handle a translation table walk requested by the Instruction side +event:0xE5 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW_PLD : Duration during which the MMU handle a translation table walk requested by a Preload instruction or Prefetch request +event:0xE6 counters:1,2,3,4,5,6 um:zero minimum:500 name:MMU_PTW_CP15 : Duration during which the MMU handle a translation table walk requested by a CP15 operation +event:0xE7 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLD_UTLB_REFILL : Level 1 PLD TLB refill +event:0xE8 counters:1,2,3,4,5,6 um:zero minimum:500 name:CP15_UTLB_REFILL : Level 1 CP15 TLB refil +event:0xE9 counters:1,2,3,4,5,6 um:zero minimum:500 name:UTLB_FLUSH : Level 1 TLB flus +event:0xEA counters:1,2,3,4,5,6 um:zero minimum:500 name:TLB_ACCESS : Level 2 TLB access +event:0xEB counters:1,2,3,4,5,6 um:zero minimum:500 name:TLB_MISS : Level 2 TLB miss diff --git a/events/arm/armv7-ca17/unit_masks b/events/arm/armv7-ca17/unit_masks new file mode 100644 index 0000000..4027469 --- /dev/null +++ b/events/arm/armv7-ca17/unit_masks @@ -0,0 +1,4 @@ +# ARM V7 PMNC possible unit masks +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index b1d5ecf..2ce0928 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -122,6 +122,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "ARM Cortex-A57", "arm/armv8-ca57", CPU_ARM_V8_CA57, 6}, { "ARM Cortex-A53", "arm/armv8-ca53", CPU_ARM_V8_CA53, 6}, { "Intel Skylake microarchitecture", "i386/skylake", CPU_SKYLAKE, 4 }, + { "ARM Cortex-A17", "arm/armv7-ca17", CPU_ARM_V7_CA17, 7 }, }; static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); @@ -411,6 +412,8 @@ static op_cpu _get_arm_cpu_type(void) return op_get_cpu_number("arm/armv7-ca9"); case 0xc0f: return op_get_cpu_number("arm/armv7-ca15"); + case 0xc0e: + return op_get_cpu_number("arm/armv7-ca17"); case 0xd07: return op_get_cpu_number("arm/armv8-ca57"); case 0xd03: diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index 9983f87..bf81130 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -102,6 +102,7 @@ typedef enum { CPU_ARM_V8_CA57, /* ARM Cortex-A57 */ CPU_ARM_V8_CA53, /* ARM Cortex-A53 */ CPU_SKYLAKE, /** < Intel Skylake microarchitecture */ + CPU_ARM_V7_CA17, /* ARM Cortex-A17 */ MAX_CPU_TYPE } op_cpu; diff --git a/libop/op_events.c b/libop/op_events.c index 25f010e..4ce1d46 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1237,6 +1237,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_ARM_V7_CA7: case CPU_ARM_V7_CA9: case CPU_ARM_V7_CA15: + case CPU_ARM_V7_CA17: case CPU_ARM_SCORPION: case CPU_ARM_SCORPIONMP: case CPU_ARM_KRAIT: diff --git a/utils/ophelp.c b/utils/ophelp.c index fdddddc..90a153e 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -629,6 +629,12 @@ int main(int argc, char const * argv[]) "Cortex A15 DDI (ARM DDI 0438F, revision r3p1)\n"; break; + case CPU_ARM_V7_CA17: + event_doc = + "See Cortex-A17 MPCore Technical Reference Manual\n" + "Cortex A17 DDI (ARM DDI 0535C, revision r1p1)\n"; + break; + case CPU_ARM_V8_APM_XGENE: event_doc = "See ARM Architecture Reference Manual \n" -- 2.34.1