From 8226fc482999342e899db0d046ad044ba2ada136 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 2 Mar 2016 23:00:21 +0000 Subject: [PATCH] AMDGPU: Simplify boolean conditional return statements Patch by Richard Thomson llvm-svn: 262536 --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 17 +++++++---------- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 5 +---- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 4 +--- llvm/lib/Target/AMDGPU/R600Packetizer.cpp | 8 ++------ llvm/lib/Target/AMDGPU/SIInsertWaits.cpp | 5 +---- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 19 ++++++------------- llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 5 +---- 7 files changed, 19 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 21716be..fb350db 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -629,16 +629,13 @@ bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const { } const Value *MemVal = N->getMemOperand()->getValue(); - if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) && - !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) && - !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) && - !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) && - !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) && - !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) && - !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) { - return true; - } - return false; + return !checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) && + !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) && + !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) && + !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) && + !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) && + !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) && + !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS); } bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index a788274..a935992 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -780,10 +780,7 @@ static bool hasDefinedInitializer(const GlobalValue *GV) { if (!GVar || !GVar->hasInitializer()) return false; - if (isa(GVar->getInitializer())) - return false; - - return true; + return !isa(GVar->getInitializer()); } SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI, diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 85a67fc..84440d1 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -905,9 +905,7 @@ bool R600InstrInfo::isPredicable(MachineInstr &MI) const { if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI)) return false; // TODO: We don't support KC merging atm - if (MI.getOperand(3).getImm() != 0 || MI.getOperand(4).getImm() != 0) - return false; - return true; + return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0; } else if (isVector(MI)) { return false; } else { diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp index 5d8ce41..964c65c 100644 --- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp @@ -178,9 +178,7 @@ public: return true; // XXX: This can be removed once the packetizer properly handles all the // LDS instruction group restrictions. - if (TII->isLDSInstr(MI.getOpcode())) - return true; - return false; + return TII->isLDSInstr(MI.getOpcode()); } // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ @@ -214,10 +212,8 @@ public: TII->definesAddressRegister(MIJ); bool ARUse = TII->usesAddressRegister(MII) || TII->usesAddressRegister(MIJ); - if (ARDef && ARUse) - return false; - return true; + return !ARDef || !ARUse; } // isLegalToPruneDependencies - Is it legal to prune dependece between SUI diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp index 65cff9c..58bfbd9 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -247,10 +247,7 @@ bool SIInsertWaits::isOpRelevant(MachineOperand &Op) { return true; MachineOperand *Data1 = TII->getNamedOperand(MI, AMDGPU::OpName::data1); - if (Data1 && Op.isIdenticalTo(*Data1)) - return true; - - return false; + return Data1 && Op.isIdenticalTo(*Data1); } // NOTE: This assumes that the value operand is before the diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 634b65d..5c9e814 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -305,11 +305,8 @@ bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt, if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt)) return true; - if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) && - (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt))) - return true; - - return false; + return (isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) && + (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)); } void @@ -1400,14 +1397,10 @@ bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI, return true; // SGPRs use the constant bus - if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC || - (!MO.isImplicit() && - (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) || - AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) { - return true; - } - - return false; + return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 || + (!MO.isImplicit() && + (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) || + AMDGPU::SGPR_64RegClass.contains(MO.getReg())))); } static unsigned findImplicitSGPRRead(const MachineInstr &MI) { diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index c8cac80..a7e1299 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -125,10 +125,7 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) return false; - if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) - return false; - - return true; + return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp); } /// \brief This function checks \p MI for operands defined by a move immediate -- 2.7.4