From 821a59588b5bddb1fe092291910ecf2744e1e49f Mon Sep 17 00:00:00 2001 From: Danila Malyutin Date: Fri, 23 Dec 2022 19:47:31 +0300 Subject: [PATCH] [TwoAddressInstruction] Constrain RegClass when processing a statepoint This transformation could've triggered a verifier assert if RegA and RegB were of different reg classes. Fix this by constraining as the comment for replaceRegWith suggests. Differential Revision: https://reviews.llvm.org/D140672 --- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 7 +++++ llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir | 33 ++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 78bf030..8cb3667a 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1681,6 +1681,13 @@ bool TwoAddressInstructionPass::processStatepoint( continue; } + if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) { + LLVM_DEBUG(dbgs() << "MRI: couldn't constrain" << printReg(RegB, TRI, 0) + << " to register class of " << printReg(RegA, TRI, 0) + << '\n'); + NeedCopy = true; + continue; + } MRI->replaceRegWith(RegA, RegB); if (LIS) { diff --git a/llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir b/llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir new file mode 100644 index 0000000..55b3e84 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir @@ -0,0 +1,33 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-unknown-linux -run-pass=twoaddressinstruction -verify-machineinstrs %s -o - | FileCheck %s +# REQUIRES: aarch64-registered-target + +# Verify that the register class is correctly constrained after the twoaddress replacement +--- +name: statepoint_twoaddr +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -4, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } +body: | + bb.0: + liveins: $w0 + + ; CHECK-LABEL: name: statepoint_twoaddr + ; CHECK: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY killed $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $xzr + ; CHECK-NEXT: [[STATEPOINT:%[0-9]+]]:gpr64sp = STATEPOINT 2882400000, 0, 1, killed [[COPY1]], undef $x0, 2, 125, 2, 4, 2, 0, 2, 2, killed [[STATEPOINT]](tied-def 0), 2, 4278124286, 2, 0, 2, 2, 0, 0, 1, 1, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead $x0, implicit-def dead early-clobber $lr :: (volatile load store (s32) on %stack.0) + ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri killed [[STATEPOINT]], 16, 0 + ; CHECK-NEXT: $x0 = COPY killed [[ADDXri]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 + %0:gpr64all = COPY killed $x0 + %1:gpr32 = COPY $xzr + %2:gpr64sp = STATEPOINT 2882400000, 0, 1, killed %1, undef $x0, 2, 125, 2, 4, 2, 0, 2, 2, killed %0(tied-def 0), 2, 4278124286, 2, 0, 2, 2, 0, 0, 1, 1, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead $x0, implicit-def dead early-clobber $lr :: (volatile load store (s32) on %stack.0) + %3:gpr64sp = ADDXri killed %2, 16, 0 + $x0 = COPY killed %3 + RET_ReallyLR implicit $x0 +... -- 2.7.4