From 8199c8a865840ef3c426d6c37ade2199a0a86812 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Wed, 10 Sep 2008 07:14:28 -0700 Subject: [PATCH] re PR target/37434 (ICE in extract_insn, at recog.c:2027) gcc/ 2008-09-10 H.J. Lu PR target/37434: * config/i386/i386.c (ix86_expand_vector_init_interleave): Force the even element into register. (ix86_expand_vector_init_general): Don't use ix86_expand_vector_init_interleave on V16QImode and V8HImode if we can't move from GPR to SSE register directly. gcc/testsuite/ 2008-09-10 H.J. Lu PR target/37434: * gcc.target/i386/pr37434-1.c: New. * gcc.target/i386/pr37434-2.c: Likewise. * gcc.target/i386/pr37434-3.c: Likewise. * gcc.target/i386/pr37434-4.c: Likewise. * gcc.target/i386/sse2-set-v8hi-1a.c: Likewise. * gcc.target/i386/sse2-set-v8hi-2a.c: Likewise. * gcc.target/i386/sse4_1-set-v16qi-1a.c: Likewise. * gcc.target/i386/sse4_1-set-v16qi-2a.c: Likewise. * gcc.target/i386/sse4_1-set-v16qi-3a.c: Likewise. From-SVN: r140231 --- gcc/ChangeLog | 17 +++++++++++++---- gcc/config/i386/i386.c | 13 +++++++++++-- gcc/testsuite/ChangeLog | 15 ++++++++++++++- gcc/testsuite/gcc.target/i386/pr37434-1.c | 12 ++++++++++++ gcc/testsuite/gcc.target/i386/pr37434-2.c | 14 ++++++++++++++ gcc/testsuite/gcc.target/i386/pr37434-3.c | 18 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr37434-4.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c | 7 +++++++ gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c | 7 +++++++ gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c | 8 ++++++++ gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c | 8 ++++++++ gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c | 8 ++++++++ 12 files changed, 140 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr37434-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr37434-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr37434-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pr37434-4.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4d68e22..5b2ecb9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2008-09-10 H.J. Lu + + PR target/37434: + * config/i386/i386.c (ix86_expand_vector_init_interleave): Force + the even element into register. + (ix86_expand_vector_init_general): Don't use + ix86_expand_vector_init_interleave on V16QImode and V8HImode + if we can't move from GPR to SSE register directly. + 2008-09-10 Bernd Schmidt * config/bfin/bfin.c (workaround_speculation): Correct algorithm to @@ -168,7 +177,7 @@ 2008-09-09 Andrey Belevantsev - PR rtl-optimization/37360 + PR rtl-optimization/37360 * haifa-sched.c (max_issue): Do not assert that we never issue more insns than issue_rate. Add comment. @@ -312,19 +321,19 @@ 2008-09-07 Helge Deller - * pa/linux-atomic.c: New file. + * pa/linux-atomic.c: New file. * pa/t-linux (LIB2FUNCS_STATIC_EXTRA): Define. * pa/t-linux64 (LIB2FUNCS_STATIC_EXTRA): Define. 2008-09-07 Richard Guenther - Ira Rosen + Ira Rosen PR tree-optimization/36630 * tree-vect-transform.c (vect_update_ivs_after_vectorizer): Call STRIP_NOPS before calling evolution_part_in_loop_num. 2008-09-07 Dorit Nuzman - Ira Rosen + Ira Rosen PR tree-optimization/35642 * config/rs6000/altivec.md (mulv8hi3): Implement. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index e847a11..3662d96 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -26886,7 +26886,7 @@ static void ix86_expand_vector_init_interleave (enum machine_mode mode, rtx target, rtx *ops, int n) { - enum machine_mode first_imode, second_imode, third_imode; + enum machine_mode first_imode, second_imode, third_imode, inner_mode; int i, j; rtx op0, op1; rtx (*gen_load_even) (rtx, rtx, rtx); @@ -26899,6 +26899,7 @@ ix86_expand_vector_init_interleave (enum machine_mode mode, gen_load_even = gen_vec_setv8hi; gen_interleave_first_low = gen_vec_interleave_lowv4si; gen_interleave_second_low = gen_vec_interleave_lowv2di; + inner_mode = HImode; first_imode = V4SImode; second_imode = V2DImode; third_imode = VOIDmode; @@ -26907,6 +26908,7 @@ ix86_expand_vector_init_interleave (enum machine_mode mode, gen_load_even = gen_vec_setv16qi; gen_interleave_first_low = gen_vec_interleave_lowv8hi; gen_interleave_second_low = gen_vec_interleave_lowv4si; + inner_mode = QImode; first_imode = V8HImode; second_imode = V4SImode; third_imode = V2DImode; @@ -26935,7 +26937,9 @@ ix86_expand_vector_init_interleave (enum machine_mode mode, emit_move_insn (op0, gen_lowpart (mode, op1)); /* Load even elements into the second positon. */ - emit_insn ((*gen_load_even) (op0, ops [i + i + 1], + emit_insn ((*gen_load_even) (op0, + force_reg (inner_mode, + ops [i + i + 1]), const1_rtx)); /* Cast vector to FIRST_IMODE vector. */ @@ -27053,6 +27057,11 @@ half: if (!TARGET_SSE2) break; + /* Don't use ix86_expand_vector_init_interleave if we can't + move from GPR to SSE register directly. */ + if (!TARGET_INTER_UNIT_MOVES) + break; + n = GET_MODE_NUNITS (mode); for (i = 0; i < n; i++) ops[i] = XVECEXP (vals, 0, i); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f78e376..f6a5b2b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2008-09-10 H.J. Lu + + PR target/37434: + * gcc.target/i386/pr37434-1.c: New. + * gcc.target/i386/pr37434-2.c: Likewise. + * gcc.target/i386/pr37434-3.c: Likewise. + * gcc.target/i386/pr37434-4.c: Likewise. + * gcc.target/i386/sse2-set-v8hi-1a.c: Likewise. + * gcc.target/i386/sse2-set-v8hi-2a.c: Likewise. + * gcc.target/i386/sse4_1-set-v16qi-1a.c: Likewise. + * gcc.target/i386/sse4_1-set-v16qi-2a.c: Likewise. + * gcc.target/i386/sse4_1-set-v16qi-3a.c: Likewise. + 2008-09-10 Tobias Burnus PR fortran/37420 @@ -631,7 +644,7 @@ * gcc.target/mips/octeon-bbit-3.c: New test. 2008-08-28 Manuel Lopez-Ibanez - Andrew Pinski + Andrew Pinski PR 18050 * gcc.dg/Wsequence-point-pr18050.c: New. diff --git a/gcc/testsuite/gcc.target/i386/pr37434-1.c b/gcc/testsuite/gcc.target/i386/pr37434-1.c new file mode 100644 index 0000000..b556bf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr37434-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const short *val ) { + short D2073 = *val; + short D2076 = *(val + 2); + short D2079 = *(val + 4); + __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0}; + return (__m128i)D2094; +} diff --git a/gcc/testsuite/gcc.target/i386/pr37434-2.c b/gcc/testsuite/gcc.target/i386/pr37434-2.c new file mode 100644 index 0000000..00ff9fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr37434-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2 -msse2" } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const short *val ) { + short D2073 = *val; + short D2076 = *(val + 2); + short D2079 = *(val + 4); + __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0}; + return (__m128i)D2094; +} + +/* { dg-final { scan-assembler "pinsrw" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr37434-3.c b/gcc/testsuite/gcc.target/i386/pr37434-3.c new file mode 100644 index 0000000..916c99f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr37434-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +typedef char __v16qi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const char *val ) { + char D2073 = *val; + char D2074 = *(val + 1); + char D2075 = *(val + 2); + char D2076 = *(val + 3); + char D2077 = *(val + 4); + char D2078 = *(val + 5); + char D2079 = *(val + 6); + __v16qi D2094 = {D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0, + D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0}; + return (__m128i)D2094; +} diff --git a/gcc/testsuite/gcc.target/i386/pr37434-4.c b/gcc/testsuite/gcc.target/i386/pr37434-4.c new file mode 100644 index 0000000..15f8292 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr37434-4.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +typedef char __v16qi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const char *val ) { + char D2073 = *val; + char D2074 = *(val + 1); + char D2075 = *(val + 2); + char D2076 = *(val + 3); + char D2077 = *(val + 4); + char D2078 = *(val + 5); + char D2079 = *(val + 6); + __v16qi D2094 = {D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0, + D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0}; + return (__m128i)D2094; +} + +/* { dg-final { scan-assembler "pinsrb" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c new file mode 100644 index 0000000..816c19e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c @@ -0,0 +1,7 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mtune=core2 -msse2" } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v8hi-1.h" diff --git a/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c new file mode 100644 index 0000000..b5103ac --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c @@ -0,0 +1,7 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mtune=core2 -msse2" } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v8hi-2.h" diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c new file mode 100644 index 0000000..b861296 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-1.h" diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c new file mode 100644 index 0000000..21f1692 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-2.h" diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c new file mode 100644 index 0000000..1065a84 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-3.h" -- 2.7.4