From 818431a61a45faeffdd876e55b57bc499d5f40a6 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Mon, 7 Nov 2016 14:47:25 +0000 Subject: [PATCH] [SystemZ] Fixes in SchedModels for older subtargets. IssueWidth updated to reflect the capacity of the issue unit correctly. Correct number of FX and LS units modelled (2, was 1). Review: Ulrich Weigand llvm-svn: 286109 --- llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 6 +++--- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 6aeb87f..815a41f 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -16,7 +16,7 @@ def Z13Model : SchedMachineModel { let UnsupportedFeatures = Arch11UnsupportedFeatures.List; - let IssueWidth = 6; // 2 * 3 instructions decoded per cycle. + let IssueWidth = 8; let MicroOpBufferSize = 60; // Issue queues let LoadLatency = 1; // Optimistic load latency. diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 9d74c91..fc478ad 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -16,7 +16,7 @@ def Z196Model : SchedMachineModel { let UnsupportedFeatures = Arch9UnsupportedFeatures.List; - let IssueWidth = 3; // 3 instructions decoded per cycle. + let IssueWidth = 5; let MicroOpBufferSize = 40; // Issue queues let LoadLatency = 1; // Optimistic load latency. @@ -56,8 +56,8 @@ def : WriteRes { let Latency = 20; let NumMicroOps = 0;} def : WriteRes { let Latency = 30; let NumMicroOps = 0;} // Execution units. -def Z196_FXUnit : ProcResource<1>; -def Z196_LSUnit : ProcResource<1>; +def Z196_FXUnit : ProcResource<2>; +def Z196_LSUnit : ProcResource<2>; def Z196_FPUnit : ProcResource<1>; // Subtarget specific definitions of scheduling resources. diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index 6ca6e85..133bb66 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -16,7 +16,7 @@ def ZEC12Model : SchedMachineModel { let UnsupportedFeatures = Arch10UnsupportedFeatures.List; - let IssueWidth = 3; // 3 instructions decoded per cycle. + let IssueWidth = 5; let MicroOpBufferSize = 40; // Issue queues let LoadLatency = 1; // Optimistic load latency. @@ -56,10 +56,10 @@ def : WriteRes { let Latency = 20; let NumMicroOps = 0;} def : WriteRes { let Latency = 30; let NumMicroOps = 0;} // Execution units. -def ZEC12_VBUnit : ProcResource<1>; -def ZEC12_FXUnit : ProcResource<1>; -def ZEC12_LSUnit : ProcResource<1>; +def ZEC12_FXUnit : ProcResource<2>; +def ZEC12_LSUnit : ProcResource<2>; def ZEC12_FPUnit : ProcResource<1>; +def ZEC12_VBUnit : ProcResource<1>; // Subtarget specific definitions of scheduling resources. def : WriteRes { let Latency = 1; } -- 2.7.4