From 81420f003bcbb559622dadfa4858523730b0dcd7 Mon Sep 17 00:00:00 2001 From: "sigurds@chromium.org" Date: Wed, 22 Oct 2014 11:06:22 +0000 Subject: [PATCH] Add FRINTP (round towards positive infinity) instruction. Macro Assember, assembler and simulator for ARM64 were missing FRINTP. R=rodolph.perfetta@arm.com, ulan@chromium.org Review URL: https://codereview.chromium.org/669923002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24800 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/arm64/assembler-arm64.cc | 6 +++ src/arm64/assembler-arm64.h | 3 ++ src/arm64/macro-assembler-arm64-inl.h | 6 +++ src/arm64/macro-assembler-arm64.h | 1 + src/arm64/simulator-arm64.cc | 10 ++++ test/cctest/test-assembler-arm64.cc | 89 +++++++++++++++++++++++++++++++++++ test/cctest/test-disasm-arm64.cc | 4 ++ 7 files changed, 119 insertions(+) diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc index c1213e9..076e143 100644 --- a/src/arm64/assembler-arm64.cc +++ b/src/arm64/assembler-arm64.cc @@ -1936,6 +1936,12 @@ void Assembler::frintn(const FPRegister& fd, } +void Assembler::frintp(const FPRegister& fd, const FPRegister& fn) { + DCHECK(fd.SizeInBits() == fn.SizeInBits()); + FPDataProcessing1Source(fd, fn, FRINTP); +} + + void Assembler::frintz(const FPRegister& fd, const FPRegister& fn) { DCHECK(fd.SizeInBits() == fn.SizeInBits()); diff --git a/src/arm64/assembler-arm64.h b/src/arm64/assembler-arm64.h index 9b1c5e6..53496f3 100644 --- a/src/arm64/assembler-arm64.h +++ b/src/arm64/assembler-arm64.h @@ -1663,6 +1663,9 @@ class Assembler : public AssemblerBase { // FP round to integer (nearest with ties to even). void frintn(const FPRegister& fd, const FPRegister& fn); + // FP round to integer (towards plus infinity). + void frintp(const FPRegister& fd, const FPRegister& fn); + // FP round to integer (towards zero.) void frintz(const FPRegister& fd, const FPRegister& fn); diff --git a/src/arm64/macro-assembler-arm64-inl.h b/src/arm64/macro-assembler-arm64-inl.h index 23767e4..22c49ef 100644 --- a/src/arm64/macro-assembler-arm64-inl.h +++ b/src/arm64/macro-assembler-arm64-inl.h @@ -825,6 +825,12 @@ void MacroAssembler::Frintn(const FPRegister& fd, const FPRegister& fn) { } +void MacroAssembler::Frintp(const FPRegister& fd, const FPRegister& fn) { + DCHECK(allow_macro_instructions_); + frintp(fd, fn); +} + + void MacroAssembler::Frintz(const FPRegister& fd, const FPRegister& fn) { DCHECK(allow_macro_instructions_); frintz(fd, fn); diff --git a/src/arm64/macro-assembler-arm64.h b/src/arm64/macro-assembler-arm64.h index d53121a..99e6d37 100644 --- a/src/arm64/macro-assembler-arm64.h +++ b/src/arm64/macro-assembler-arm64.h @@ -422,6 +422,7 @@ class MacroAssembler : public Assembler { inline void Frinta(const FPRegister& fd, const FPRegister& fn); inline void Frintm(const FPRegister& fd, const FPRegister& fn); inline void Frintn(const FPRegister& fd, const FPRegister& fn); + inline void Frintp(const FPRegister& fd, const FPRegister& fn); inline void Frintz(const FPRegister& fd, const FPRegister& fn); inline void Fsqrt(const FPRegister& fd, const FPRegister& fn); inline void Fsub(const FPRegister& fd, diff --git a/src/arm64/simulator-arm64.cc b/src/arm64/simulator-arm64.cc index 129252b..569be9c 100644 --- a/src/arm64/simulator-arm64.cc +++ b/src/arm64/simulator-arm64.cc @@ -2463,6 +2463,12 @@ void Simulator::VisitFPDataProcessing1Source(Instruction* instr) { set_sreg(fd, FPRoundInt(sreg(fn), FPNegativeInfinity)); break; case FRINTM_d: set_dreg(fd, FPRoundInt(dreg(fn), FPNegativeInfinity)); break; + case FRINTP_s: + set_sreg(fd, FPRoundInt(sreg(fn), FPPositiveInfinity)); + break; + case FRINTP_d: + set_dreg(fd, FPRoundInt(dreg(fn), FPPositiveInfinity)); + break; case FRINTN_s: set_sreg(fd, FPRoundInt(sreg(fn), FPTieEven)); break; case FRINTN_d: set_dreg(fd, FPRoundInt(dreg(fn), FPTieEven)); break; case FRINTZ_s: set_sreg(fd, FPRoundInt(sreg(fn), FPZero)); break; @@ -2767,6 +2773,10 @@ double Simulator::FPRoundInt(double value, FPRounding round_mode) { // We always use floor(value). break; } + case FPPositiveInfinity: { + int_result = ceil(value); + break; + } default: UNIMPLEMENTED(); } return int_result; diff --git a/test/cctest/test-assembler-arm64.cc b/test/cctest/test-assembler-arm64.cc index 587a4ce..108152e 100644 --- a/test/cctest/test-assembler-arm64.cc +++ b/test/cctest/test-assembler-arm64.cc @@ -6554,6 +6554,95 @@ TEST(frintn) { } +TEST(frintp) { + INIT_V8(); + SETUP(); + + START(); + __ Fmov(s16, 1.0); + __ Fmov(s17, 1.1); + __ Fmov(s18, 1.5); + __ Fmov(s19, 1.9); + __ Fmov(s20, 2.5); + __ Fmov(s21, -1.5); + __ Fmov(s22, -2.5); + __ Fmov(s23, kFP32PositiveInfinity); + __ Fmov(s24, kFP32NegativeInfinity); + __ Fmov(s25, 0.0); + __ Fmov(s26, -0.0); + __ Fmov(s27, -0.2); + + __ Frintp(s0, s16); + __ Frintp(s1, s17); + __ Frintp(s2, s18); + __ Frintp(s3, s19); + __ Frintp(s4, s20); + __ Frintp(s5, s21); + __ Frintp(s6, s22); + __ Frintp(s7, s23); + __ Frintp(s8, s24); + __ Frintp(s9, s25); + __ Frintp(s10, s26); + __ Frintp(s11, s27); + + __ Fmov(d16, -0.5); + __ Fmov(d17, -0.8); + __ Fmov(d18, 1.5); + __ Fmov(d19, 1.9); + __ Fmov(d20, 2.5); + __ Fmov(d21, -1.5); + __ Fmov(d22, -2.5); + __ Fmov(d23, kFP32PositiveInfinity); + __ Fmov(d24, kFP32NegativeInfinity); + __ Fmov(d25, 0.0); + __ Fmov(d26, -0.0); + __ Fmov(d27, -0.2); + + __ Frintp(d12, d16); + __ Frintp(d13, d17); + __ Frintp(d14, d18); + __ Frintp(d15, d19); + __ Frintp(d16, d20); + __ Frintp(d17, d21); + __ Frintp(d18, d22); + __ Frintp(d19, d23); + __ Frintp(d20, d24); + __ Frintp(d21, d25); + __ Frintp(d22, d26); + __ Frintp(d23, d27); + END(); + + RUN(); + + CHECK_EQUAL_FP32(1.0, s0); + CHECK_EQUAL_FP32(2.0, s1); + CHECK_EQUAL_FP32(2.0, s2); + CHECK_EQUAL_FP32(2.0, s3); + CHECK_EQUAL_FP32(3.0, s4); + CHECK_EQUAL_FP32(-1.0, s5); + CHECK_EQUAL_FP32(-2.0, s6); + CHECK_EQUAL_FP32(kFP32PositiveInfinity, s7); + CHECK_EQUAL_FP32(kFP32NegativeInfinity, s8); + CHECK_EQUAL_FP32(0.0, s9); + CHECK_EQUAL_FP32(-0.0, s10); + CHECK_EQUAL_FP32(-0.0, s11); + CHECK_EQUAL_FP64(-0.0, d12); + CHECK_EQUAL_FP64(-0.0, d13); + CHECK_EQUAL_FP64(2.0, d14); + CHECK_EQUAL_FP64(2.0, d15); + CHECK_EQUAL_FP64(3.0, d16); + CHECK_EQUAL_FP64(-1.0, d17); + CHECK_EQUAL_FP64(-2.0, d18); + CHECK_EQUAL_FP64(kFP64PositiveInfinity, d19); + CHECK_EQUAL_FP64(kFP64NegativeInfinity, d20); + CHECK_EQUAL_FP64(0.0, d21); + CHECK_EQUAL_FP64(-0.0, d22); + CHECK_EQUAL_FP64(-0.0, d23); + + TEARDOWN(); +} + + TEST(frintz) { INIT_V8(); SETUP(); diff --git a/test/cctest/test-disasm-arm64.cc b/test/cctest/test-disasm-arm64.cc index fb01347..208f1f5 100644 --- a/test/cctest/test-disasm-arm64.cc +++ b/test/cctest/test-disasm-arm64.cc @@ -1408,6 +1408,10 @@ TEST_(fp_dp1) { COMPARE(frintn(s31, s30), "frintn s31, s30"); COMPARE(frintn(d12, d13), "frintn d12, d13"); COMPARE(frintn(d31, d30), "frintn d31, d30"); + COMPARE(frintp(s10, s11), "frintp s10, s11"); + COMPARE(frintp(s31, s30), "frintp s31, s30"); + COMPARE(frintp(d12, d13), "frintp d12, d13"); + COMPARE(frintp(d31, d30), "frintp d31, d30"); COMPARE(frintz(s10, s11), "frintz s10, s11"); COMPARE(frintz(s31, s30), "frintz s31, s30"); COMPARE(frintz(d12, d13), "frintz d12, d13"); -- 2.7.4