From 80cd8da78d027f59b54586887af4bb9c3b36a6ba Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Fri, 1 Oct 2021 16:52:51 +0300 Subject: [PATCH] [X86][Costmodel] Load/store i32/f32 Stride=2 VF=16 interleaving costs The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/M9eev3xe8 - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=4.0` So pick cost of `8`. For store we have: https://godbolt.org/z/M9eev3xe8 - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: =4.0` So pick cost of `8`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D110756 --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 2 ++ llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll | 2 +- 5 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 8bfdb61..87c9c4f 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5078,6 +5078,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 + {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 @@ -5125,6 +5126,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) + {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll index 34e5104..a927bd6 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll @@ -29,7 +29,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: %v0 = load float, float* %in0, align 4 -; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction: %v0 = load float, float* %in0, align 4 +; AVX2: LV: Found an estimated cost of 12 for VF 16 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 152 for VF 32 For instruction: %v0 = load float, float* %in0, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load float, float* %in0, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll index 339b06d..1270c9f 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll @@ -29,7 +29,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: %v0 = load i32, i32* %in0, align 4 -; AVX2: LV: Found an estimated cost of 92 for VF 16 For instruction: %v0 = load i32, i32* %in0, align 4 +; AVX2: LV: Found an estimated cost of 12 for VF 16 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 184 for VF 32 For instruction: %v0 = load i32, i32* %in0, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i32, i32* %in0, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll index cb01b28..e09e40f 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll @@ -29,7 +29,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 2 for VF 2 For instruction: store float %v1, float* %out1, align 4 ; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: store float %v1, float* %out1, align 4 ; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: store float %v1, float* %out1, align 4 -; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction: store float %v1, float* %out1, align 4 +; AVX2: LV: Found an estimated cost of 12 for VF 16 For instruction: store float %v1, float* %out1, align 4 ; AVX2: LV: Found an estimated cost of 152 for VF 32 For instruction: store float %v1, float* %out1, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v1, float* %out1, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll index a26792f..5b9ae5f 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll @@ -29,7 +29,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 2 for VF 2 For instruction: store i32 %v1, i32* %out1, align 4 ; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: store i32 %v1, i32* %out1, align 4 ; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: store i32 %v1, i32* %out1, align 4 -; AVX2: LV: Found an estimated cost of 92 for VF 16 For instruction: store i32 %v1, i32* %out1, align 4 +; AVX2: LV: Found an estimated cost of 12 for VF 16 For instruction: store i32 %v1, i32* %out1, align 4 ; AVX2: LV: Found an estimated cost of 184 for VF 32 For instruction: store i32 %v1, i32* %out1, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v1, i32* %out1, align 4 -- 2.7.4