From 8076c70d6a2a21d18713458996732f5231d61f43 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 16 Nov 2022 13:13:53 -0500 Subject: [PATCH] [SystemZ] change test to mir to better isolate miscompile; NFC --- llvm/test/CodeGen/SystemZ/merge-stores.ll | 36 ++++++++++++++++--------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/llvm/test/CodeGen/SystemZ/merge-stores.ll b/llvm/test/CodeGen/SystemZ/merge-stores.ll index 7473258..73b2df8 100644 --- a/llvm/test/CodeGen/SystemZ/merge-stores.ll +++ b/llvm/test/CodeGen/SystemZ/merge-stores.ll @@ -1,5 +1,5 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=s390x-linux-gnu -pre-RA-sched=list-ilp -disable-sched-live-uses=false | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc < %s -mtriple=s390x-linux-gnu -stop-after finalize-isel | FileCheck %s target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" @@ -9,23 +9,25 @@ target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" @f = dso_local local_unnamed_addr global ptr @e, align 8 @d = dso_local local_unnamed_addr global i32 0, align 4 -; FIXME: This shows a miscompile caused by merging truncated -; stores if the store of 0 (sthrl) to 'e' happens before -; a 64-bit store (stg) of r0. +; FIXME: This shows a miscompile caused by merging truncated +; stores if there is a 64-bit store (stg) of the load from '@e'. define signext i32 @main() { -; CHECK-LABEL: main: -; CHECK: # %bb.0: -; CHECK-NEXT: lgrl %r0, e -; CHECK-NEXT: lgrl %r1, f -; CHECK-NEXT: srlg %r2, %r0, 32 -; CHECK-NEXT: st %r2, 0(%r1) -; CHECK-NEXT: lhi %r2, 0 -; CHECK-NEXT: sthrl %r2, e -; CHECK-NEXT: stg %r0, 0(%r1) -; CHECK-NEXT: lghi %r2, 0 -; CHECK-NEXT: strl %r0, d -; CHECK-NEXT: br %r14 + ; CHECK-LABEL: name: main + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: [[LGRL:%[0-9]+]]:gr64bit = LGRL @e :: (dereferenceable load (s64) from @e) + ; CHECK-NEXT: [[SRLG:%[0-9]+]]:gr64bit = SRLG [[LGRL]], $noreg, 32 + ; CHECK-NEXT: [[LGRL1:%[0-9]+]]:addr64bit = LGRL @f :: (dereferenceable load (s64) from @f) + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32bit = COPY [[SRLG]].subreg_l32 + ; CHECK-NEXT: ST killed [[COPY]], [[LGRL1]], 0, $noreg :: (store (s32) into %ir.t1) + ; CHECK-NEXT: STG [[LGRL]], [[LGRL1]], 0, $noreg :: (store (s64) into %ir.t1, align 4) + ; CHECK-NEXT: [[LHI:%[0-9]+]]:gr32bit = LHI 0 + ; CHECK-NEXT: STHRL killed [[LHI]], @e :: (store (s16) into @e, align 8) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32bit = COPY [[LGRL]].subreg_l32 + ; CHECK-NEXT: STRL killed [[COPY1]], @d :: (store (s32) into @d) + ; CHECK-NEXT: [[LGHI:%[0-9]+]]:gr64bit = LGHI 0 + ; CHECK-NEXT: $r2d = COPY [[LGHI]] + ; CHECK-NEXT: Return implicit $r2d %e = load i64, ptr @e, align 8 %esh = lshr i64 %e, 32 %ehi = trunc i64 %esh to i32 -- 2.7.4