From 805b72e613316049fcb0c19635993b7f668f0d8f Mon Sep 17 00:00:00 2001
From: Doug Evans <dje@google.com>
Date: Thu, 28 Jan 1999 06:18:23 +0000
Subject: [PATCH] 	* fr30-opc.h,fr30-opc.c: Rebuild. 	*
 i960c-opc.h,i960c-opc.c: Rebuild. 	* m32r-opc.c: Rebuild.

---
 opcodes/ChangeLog   |    6 +
 opcodes/i960c-opc.c | 1210 +++++++++++++--------------------------------------
 opcodes/i960c-opc.h |    2 +-
 opcodes/m32r-opc.c  |  768 ++++++++++++++------------------
 4 files changed, 635 insertions(+), 1351 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 93bcea8..3c073a8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+1999-01-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* fr30-opc.h,fr30-opc.c: Rebuild.
+	* i960c-opc.h,i960c-opc.c: Rebuild.
+	* m32r-opc.c: Rebuild.
+
 Tue Jan 19 18:01:54 1999  David Taylor  <taylor@texas.cygnus.com>
 
 	* hppa-dis.c: revert HP merge changes until HP gives us
diff --git a/opcodes/i960c-opc.c b/opcodes/i960c-opc.c
index f2c7f69..b9bd1b4 100644
--- a/opcodes/i960c-opc.c
+++ b/opcodes/i960c-opc.c
@@ -442,678 +442,62 @@ const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
 
 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
 
-static const CGEN_IFMT fmt_empty = {
+static const CGEN_IFMT ifmt_empty = {
   0, 0, 0x0, { 0 }
 };
 
-static const CGEN_IFMT fmt_mulo = {
+static const CGEN_IFMT ifmt_mulo = {
   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 };
 
-static const CGEN_IFMT fmt_mulo1 = {
+static const CGEN_IFMT ifmt_mulo1 = {
   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 };
 
-static const CGEN_IFMT fmt_mulo2 = {
+static const CGEN_IFMT ifmt_mulo2 = {
   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 };
 
-static const CGEN_IFMT fmt_mulo3 = {
+static const CGEN_IFMT ifmt_mulo3 = {
   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 };
 
-static const CGEN_IFMT fmt_remo = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_remo1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_remo2 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_remo3 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_not = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_not1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_not2 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_not3 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_emul = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_emul1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_emul2 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_emul3 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_movl = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_movl1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_movt = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_movt1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_movq = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_movq1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_modpc = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_lda_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldob_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldos_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldib_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldis_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldl_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldt_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_ldq_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_st_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_st_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_st_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_st_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_st_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_st_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_st_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_st_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stob_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stos_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stos_indirect_offset = {
+static const CGEN_IFMT ifmt_lda_offset = {
   32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
 };
 
-static const CGEN_IFMT fmt_stos_indirect = {
+static const CGEN_IFMT ifmt_lda_indirect = {
   32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 };
 
-static const CGEN_IFMT fmt_stos_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stos_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stos_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stos_index_disp = {
+static const CGEN_IFMT ifmt_lda_disp = {
   32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 };
 
-static const CGEN_IFMT fmt_stos_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stl_offset = {
+static const CGEN_IFMT ifmt_st_offset = {
   32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
 };
 
-static const CGEN_IFMT fmt_stl_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stl_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stl_indirect_index = {
+static const CGEN_IFMT ifmt_st_indirect = {
   32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 };
 
-static const CGEN_IFMT fmt_stl_disp = {
+static const CGEN_IFMT ifmt_st_disp = {
   32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 };
 
-static const CGEN_IFMT fmt_stl_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stl_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stl_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stt_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_stq_indirect_index_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpobe_reg = {
-  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpobe_lit = {
-  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpobl_reg = {
+static const CGEN_IFMT ifmt_cmpobe_reg = {
   32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
 };
 
-static const CGEN_IFMT fmt_cmpobl_lit = {
+static const CGEN_IFMT ifmt_cmpobe_lit = {
   32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
 };
 
-static const CGEN_IFMT fmt_bbc_lit = {
-  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpi = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpi1 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpi2 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_cmpi3 = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_testno_reg = {
-  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
-};
-
-static const CGEN_IFMT fmt_bno = {
+static const CGEN_IFMT ifmt_bno = {
   32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
 };
 
-static const CGEN_IFMT fmt_b = {
-  32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
-};
-
-static const CGEN_IFMT fmt_bx_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_bx_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_bx_indirect_index = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_bx_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_bx_indirect_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_callx_disp = {
-  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_callx_indirect = {
-  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
-};
-
-static const CGEN_IFMT fmt_callx_indirect_offset = {
-  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
-};
-
-static const CGEN_IFMT fmt_ret = {
-  32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
-};
-
-static const CGEN_IFMT fmt_calls = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_fmark = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
-static const CGEN_IFMT fmt_flushreg = {
-  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
-};
-
 #undef F
 
 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
@@ -1135,7 +519,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MULO, "mulo", "mulo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x70000080 },
+    & ifmt_mulo, { 0x70000080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1144,7 +528,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MULO1, "mulo1", "mulo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x70000880 },
+    & ifmt_mulo1, { 0x70000880 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1153,7 +537,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MULO2, "mulo2", "mulo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x70001080 },
+    & ifmt_mulo2, { 0x70001080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1162,7 +546,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MULO3, "mulo3", "mulo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x70001880 },
+    & ifmt_mulo3, { 0x70001880 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1171,7 +555,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMO, "remo", "remo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x70000400 },
+    & ifmt_mulo, { 0x70000400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1180,7 +564,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMO1, "remo1", "remo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x70000c00 },
+    & ifmt_mulo1, { 0x70000c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1189,7 +573,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMO2, "remo2", "remo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x70001400 },
+    & ifmt_mulo2, { 0x70001400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1198,7 +582,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMO3, "remo3", "remo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x70001c00 },
+    & ifmt_mulo3, { 0x70001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1207,7 +591,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVO, "divo", "divo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x70000580 },
+    & ifmt_mulo, { 0x70000580 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1216,7 +600,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVO1, "divo1", "divo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x70000d80 },
+    & ifmt_mulo1, { 0x70000d80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1225,7 +609,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVO2, "divo2", "divo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x70001580 },
+    & ifmt_mulo2, { 0x70001580 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1234,7 +618,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVO3, "divo3", "divo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x70001d80 },
+    & ifmt_mulo3, { 0x70001d80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1243,7 +627,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMI, "remi", "remi",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x74000400 },
+    & ifmt_mulo, { 0x74000400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1252,7 +636,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMI1, "remi1", "remi",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x74000c00 },
+    & ifmt_mulo1, { 0x74000c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1261,7 +645,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMI2, "remi2", "remi",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x74001400 },
+    & ifmt_mulo2, { 0x74001400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1270,7 +654,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_REMI3, "remi3", "remi",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x74001c00 },
+    & ifmt_mulo3, { 0x74001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1279,7 +663,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVI, "divi", "divi",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x74000580 },
+    & ifmt_mulo, { 0x74000580 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1288,7 +672,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVI1, "divi1", "divi",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x74000d80 },
+    & ifmt_mulo1, { 0x74000d80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1297,7 +681,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVI2, "divi2", "divi",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x74001580 },
+    & ifmt_mulo2, { 0x74001580 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1306,7 +690,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_DIVI3, "divi3", "divi",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x74001d80 },
+    & ifmt_mulo3, { 0x74001d80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1315,7 +699,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ADDO, "addo", "addo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x59000000 },
+    & ifmt_mulo, { 0x59000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1324,7 +708,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ADDO1, "addo1", "addo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x59000800 },
+    & ifmt_mulo1, { 0x59000800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1333,7 +717,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ADDO2, "addo2", "addo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x59001000 },
+    & ifmt_mulo2, { 0x59001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1342,7 +726,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ADDO3, "addo3", "addo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x59001800 },
+    & ifmt_mulo3, { 0x59001800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1351,7 +735,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SUBO, "subo", "subo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x59000100 },
+    & ifmt_mulo, { 0x59000100 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1360,7 +744,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SUBO1, "subo1", "subo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x59000900 },
+    & ifmt_mulo1, { 0x59000900 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1369,7 +753,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SUBO2, "subo2", "subo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x59001100 },
+    & ifmt_mulo2, { 0x59001100 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1378,7 +762,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SUBO3, "subo3", "subo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x59001900 },
+    & ifmt_mulo3, { 0x59001900 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1387,7 +771,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTBIT, "notbit", "notbit",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x58000000 },
+    & ifmt_mulo, { 0x58000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1396,7 +780,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTBIT1, "notbit1", "notbit",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x58000800 },
+    & ifmt_mulo1, { 0x58000800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1405,7 +789,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTBIT2, "notbit2", "notbit",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x58001000 },
+    & ifmt_mulo2, { 0x58001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1414,7 +798,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTBIT3, "notbit3", "notbit",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x58001800 },
+    & ifmt_mulo3, { 0x58001800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1423,7 +807,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_AND, "and", "and",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x58000080 },
+    & ifmt_mulo, { 0x58000080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1432,7 +816,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_AND1, "and1", "and",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x58000880 },
+    & ifmt_mulo1, { 0x58000880 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1441,7 +825,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_AND2, "and2", "and",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x58001080 },
+    & ifmt_mulo2, { 0x58001080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1450,7 +834,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_AND3, "and3", "and",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x58001880 },
+    & ifmt_mulo3, { 0x58001880 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1459,7 +843,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ANDNOT, "andnot", "andnot",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x58000100 },
+    & ifmt_mulo, { 0x58000100 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1468,7 +852,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ANDNOT1, "andnot1", "andnot",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x58000900 },
+    & ifmt_mulo1, { 0x58000900 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1477,7 +861,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ANDNOT2, "andnot2", "andnot",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x58001100 },
+    & ifmt_mulo2, { 0x58001100 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1486,7 +870,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ANDNOT3, "andnot3", "andnot",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x58001900 },
+    & ifmt_mulo3, { 0x58001900 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1495,7 +879,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SETBIT, "setbit", "setbit",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x58000180 },
+    & ifmt_mulo, { 0x58000180 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1504,7 +888,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SETBIT1, "setbit1", "setbit",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x58000980 },
+    & ifmt_mulo1, { 0x58000980 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1513,7 +897,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SETBIT2, "setbit2", "setbit",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x58001180 },
+    & ifmt_mulo2, { 0x58001180 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1522,7 +906,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SETBIT3, "setbit3", "setbit",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x58001980 },
+    & ifmt_mulo3, { 0x58001980 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1531,7 +915,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTAND, "notand", "notand",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x58000200 },
+    & ifmt_mulo, { 0x58000200 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1540,7 +924,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTAND1, "notand1", "notand",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x58000a00 },
+    & ifmt_mulo1, { 0x58000a00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1549,7 +933,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTAND2, "notand2", "notand",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x58001200 },
+    & ifmt_mulo2, { 0x58001200 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1558,7 +942,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOTAND3, "notand3", "notand",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x58001a00 },
+    & ifmt_mulo3, { 0x58001a00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1567,7 +951,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_XOR, "xor", "xor",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x58000300 },
+    & ifmt_mulo, { 0x58000300 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1576,7 +960,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_XOR1, "xor1", "xor",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x58000b00 },
+    & ifmt_mulo1, { 0x58000b00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1585,7 +969,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_XOR2, "xor2", "xor",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x58001300 },
+    & ifmt_mulo2, { 0x58001300 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1594,7 +978,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_XOR3, "xor3", "xor",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x58001b00 },
+    & ifmt_mulo3, { 0x58001b00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1603,7 +987,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_OR, "or", "or",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x58000380 },
+    & ifmt_mulo, { 0x58000380 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1612,7 +996,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_OR1, "or1", "or",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x58000b80 },
+    & ifmt_mulo1, { 0x58000b80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1621,7 +1005,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_OR2, "or2", "or",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x58001380 },
+    & ifmt_mulo2, { 0x58001380 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1630,7 +1014,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_OR3, "or3", "or",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x58001b80 },
+    & ifmt_mulo3, { 0x58001b80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1639,7 +1023,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOR, "nor", "nor",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x58000400 },
+    & ifmt_mulo, { 0x58000400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1648,7 +1032,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOR1, "nor1", "nor",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x58000c00 },
+    & ifmt_mulo1, { 0x58000c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1657,7 +1041,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOR2, "nor2", "nor",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x58001400 },
+    & ifmt_mulo2, { 0x58001400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1666,7 +1050,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOR3, "nor3", "nor",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x58001c00 },
+    & ifmt_mulo3, { 0x58001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1675,7 +1059,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOT, "not", "not",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_not, { 0x58000500 },
+    & ifmt_mulo, { 0x58000500 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1684,7 +1068,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOT1, "not1", "not",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_not1, { 0x58000d00 },
+    & ifmt_mulo1, { 0x58000d00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1693,7 +1077,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOT2, "not2", "not",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_not2, { 0x58001500 },
+    & ifmt_mulo2, { 0x58001500 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1702,7 +1086,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_NOT3, "not3", "not",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_not3, { 0x58001d00 },
+    & ifmt_mulo3, { 0x58001d00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1711,7 +1095,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CLRBIT, "clrbit", "clrbit",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo, { 0x58000600 },
+    & ifmt_mulo, { 0x58000600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1720,7 +1104,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CLRBIT1, "clrbit1", "clrbit",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo1, { 0x58000e00 },
+    & ifmt_mulo1, { 0x58000e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1729,7 +1113,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CLRBIT2, "clrbit2", "clrbit",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo2, { 0x58001600 },
+    & ifmt_mulo2, { 0x58001600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1738,7 +1122,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CLRBIT3, "clrbit3", "clrbit",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_mulo3, { 0x58001e00 },
+    & ifmt_mulo3, { 0x58001e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1747,7 +1131,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLO, "shlo", "shlo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x59000600 },
+    & ifmt_mulo, { 0x59000600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1756,7 +1140,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLO1, "shlo1", "shlo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x59000e00 },
+    & ifmt_mulo1, { 0x59000e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1765,7 +1149,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLO2, "shlo2", "shlo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x59001600 },
+    & ifmt_mulo2, { 0x59001600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1774,7 +1158,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLO3, "shlo3", "shlo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x59001e00 },
+    & ifmt_mulo3, { 0x59001e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1783,7 +1167,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRO, "shro", "shro",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x59000400 },
+    & ifmt_mulo, { 0x59000400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1792,7 +1176,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRO1, "shro1", "shro",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x59000c00 },
+    & ifmt_mulo1, { 0x59000c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1801,7 +1185,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRO2, "shro2", "shro",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x59001400 },
+    & ifmt_mulo2, { 0x59001400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1810,7 +1194,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRO3, "shro3", "shro",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x59001c00 },
+    & ifmt_mulo3, { 0x59001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1819,7 +1203,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLI, "shli", "shli",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x59000700 },
+    & ifmt_mulo, { 0x59000700 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1828,7 +1212,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLI1, "shli1", "shli",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x59000f00 },
+    & ifmt_mulo1, { 0x59000f00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1837,7 +1221,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLI2, "shli2", "shli",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x59001700 },
+    & ifmt_mulo2, { 0x59001700 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1846,7 +1230,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHLI3, "shli3", "shli",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x59001f00 },
+    & ifmt_mulo3, { 0x59001f00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1855,7 +1239,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRI, "shri", "shri",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo, { 0x59000580 },
+    & ifmt_mulo, { 0x59000580 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1864,7 +1248,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRI1, "shri1", "shri",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo1, { 0x59000d80 },
+    & ifmt_mulo1, { 0x59000d80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1873,7 +1257,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRI2, "shri2", "shri",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo2, { 0x59001580 },
+    & ifmt_mulo2, { 0x59001580 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1882,7 +1266,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_SHRI3, "shri3", "shri",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_remo3, { 0x59001d80 },
+    & ifmt_mulo3, { 0x59001d80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1891,7 +1275,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_EMUL, "emul", "emul",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_emul, { 0x67000000 },
+    & ifmt_mulo, { 0x67000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1900,7 +1284,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_EMUL1, "emul1", "emul",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_emul1, { 0x67000800 },
+    & ifmt_mulo1, { 0x67000800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1909,7 +1293,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_EMUL2, "emul2", "emul",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_emul2, { 0x67001000 },
+    & ifmt_mulo2, { 0x67001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1918,7 +1302,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_EMUL3, "emul3", "emul",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
-    & fmt_emul3, { 0x67001800 },
+    & ifmt_mulo3, { 0x67001800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1927,7 +1311,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOV, "mov", "mov",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
-    & fmt_not2, { 0x5c001600 },
+    & ifmt_mulo2, { 0x5c001600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1936,7 +1320,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOV1, "mov1", "mov",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
-    & fmt_not3, { 0x5c001e00 },
+    & ifmt_mulo3, { 0x5c001e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1945,7 +1329,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOVL, "movl", "movl",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
-    & fmt_movl, { 0x5d001600 },
+    & ifmt_mulo2, { 0x5d001600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1954,7 +1338,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOVL1, "movl1", "movl",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
-    & fmt_movl1, { 0x5d001e00 },
+    & ifmt_mulo3, { 0x5d001e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1963,7 +1347,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOVT, "movt", "movt",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
-    & fmt_movt, { 0x5e001600 },
+    & ifmt_mulo2, { 0x5e001600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1972,7 +1356,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOVT1, "movt1", "movt",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
-    & fmt_movt1, { 0x5e001e00 },
+    & ifmt_mulo3, { 0x5e001e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1981,7 +1365,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOVQ, "movq", "movq",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
-    & fmt_movq, { 0x5f001600 },
+    & ifmt_mulo2, { 0x5f001600 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1990,7 +1374,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MOVQ1, "movq1", "movq",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
-    & fmt_movq1, { 0x5f001e00 },
+    & ifmt_mulo3, { 0x5f001e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -1999,7 +1383,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MODPC, "modpc", "modpc",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_modpc, { 0x65000280 },
+    & ifmt_mulo, { 0x65000280 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2008,7 +1392,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_MODAC, "modac", "modac",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
-    & fmt_modpc, { 0x64000280 },
+    & ifmt_mulo, { 0x64000280 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2017,7 +1401,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_OFFSET, "lda-offset", "lda",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_lda_offset, { 0x8c000000 },
+    & ifmt_lda_offset, { 0x8c000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2026,7 +1410,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_lda_indirect_offset, { 0x8c002000 },
+    & ifmt_lda_offset, { 0x8c002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2035,7 +1419,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_lda_indirect, { 0x8c001000 },
+    & ifmt_lda_indirect, { 0x8c001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2044,7 +1428,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_lda_indirect_index, { 0x8c001c00 },
+    & ifmt_lda_indirect, { 0x8c001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2053,7 +1437,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_DISP, "lda-disp", "lda",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_lda_disp, { 0x8c003000 },
+    & ifmt_lda_disp, { 0x8c003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2062,7 +1446,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_lda_indirect_disp, { 0x8c003400 },
+    & ifmt_lda_disp, { 0x8c003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2071,7 +1455,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_lda_index_disp, { 0x8c003800 },
+    & ifmt_lda_disp, { 0x8c003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2080,7 +1464,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_lda_indirect_index_disp, { 0x8c003c00 },
+    & ifmt_lda_disp, { 0x8c003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2089,7 +1473,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_OFFSET, "ld-offset", "ld",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ld_offset, { 0x90000000 },
+    & ifmt_lda_offset, { 0x90000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2098,7 +1482,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ld_indirect_offset, { 0x90002000 },
+    & ifmt_lda_offset, { 0x90002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2107,7 +1491,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ld_indirect, { 0x90001000 },
+    & ifmt_lda_indirect, { 0x90001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2116,7 +1500,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ld_indirect_index, { 0x90001c00 },
+    & ifmt_lda_indirect, { 0x90001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2125,7 +1509,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_DISP, "ld-disp", "ld",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ld_disp, { 0x90003000 },
+    & ifmt_lda_disp, { 0x90003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2134,7 +1518,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ld_indirect_disp, { 0x90003400 },
+    & ifmt_lda_disp, { 0x90003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2143,7 +1527,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ld_index_disp, { 0x90003800 },
+    & ifmt_lda_disp, { 0x90003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2152,7 +1536,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ld_indirect_index_disp, { 0x90003c00 },
+    & ifmt_lda_disp, { 0x90003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2161,7 +1545,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_offset, { 0x80000000 },
+    & ifmt_lda_offset, { 0x80000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2170,7 +1554,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_indirect_offset, { 0x80002000 },
+    & ifmt_lda_offset, { 0x80002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2179,7 +1563,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_indirect, { 0x80001000 },
+    & ifmt_lda_indirect, { 0x80001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2188,7 +1572,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_indirect_index, { 0x80001c00 },
+    & ifmt_lda_indirect, { 0x80001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2197,7 +1581,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_disp, { 0x80003000 },
+    & ifmt_lda_disp, { 0x80003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2206,7 +1590,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_indirect_disp, { 0x80003400 },
+    & ifmt_lda_disp, { 0x80003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2215,7 +1599,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_index_disp, { 0x80003800 },
+    & ifmt_lda_disp, { 0x80003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2224,7 +1608,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldob_indirect_index_disp, { 0x80003c00 },
+    & ifmt_lda_disp, { 0x80003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2233,7 +1617,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_offset, { 0x88000000 },
+    & ifmt_lda_offset, { 0x88000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2242,7 +1626,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_indirect_offset, { 0x88002000 },
+    & ifmt_lda_offset, { 0x88002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2251,7 +1635,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_indirect, { 0x88001000 },
+    & ifmt_lda_indirect, { 0x88001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2260,7 +1644,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_indirect_index, { 0x88001c00 },
+    & ifmt_lda_indirect, { 0x88001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2269,7 +1653,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_disp, { 0x88003000 },
+    & ifmt_lda_disp, { 0x88003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2278,7 +1662,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_indirect_disp, { 0x88003400 },
+    & ifmt_lda_disp, { 0x88003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2287,7 +1671,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_index_disp, { 0x88003800 },
+    & ifmt_lda_disp, { 0x88003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2296,7 +1680,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldos_indirect_index_disp, { 0x88003c00 },
+    & ifmt_lda_disp, { 0x88003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2305,7 +1689,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_offset, { 0xc0000000 },
+    & ifmt_lda_offset, { 0xc0000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2314,7 +1698,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_indirect_offset, { 0xc0002000 },
+    & ifmt_lda_offset, { 0xc0002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2323,7 +1707,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_indirect, { 0xc0001000 },
+    & ifmt_lda_indirect, { 0xc0001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2332,7 +1716,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_indirect_index, { 0xc0001c00 },
+    & ifmt_lda_indirect, { 0xc0001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2341,7 +1725,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_disp, { 0xc0003000 },
+    & ifmt_lda_disp, { 0xc0003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2350,7 +1734,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_indirect_disp, { 0xc0003400 },
+    & ifmt_lda_disp, { 0xc0003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2359,7 +1743,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_index_disp, { 0xc0003800 },
+    & ifmt_lda_disp, { 0xc0003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2368,7 +1752,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldib_indirect_index_disp, { 0xc0003c00 },
+    & ifmt_lda_disp, { 0xc0003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2377,7 +1761,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_offset, { 0xc8000000 },
+    & ifmt_lda_offset, { 0xc8000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2386,7 +1770,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_indirect_offset, { 0xc8002000 },
+    & ifmt_lda_offset, { 0xc8002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2395,7 +1779,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_indirect, { 0xc8001000 },
+    & ifmt_lda_indirect, { 0xc8001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2404,7 +1788,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_indirect_index, { 0xc8001c00 },
+    & ifmt_lda_indirect, { 0xc8001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2413,7 +1797,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_disp, { 0xc8003000 },
+    & ifmt_lda_disp, { 0xc8003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2422,7 +1806,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_indirect_disp, { 0xc8003400 },
+    & ifmt_lda_disp, { 0xc8003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2431,7 +1815,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_index_disp, { 0xc8003800 },
+    & ifmt_lda_disp, { 0xc8003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2440,7 +1824,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldis_indirect_index_disp, { 0xc8003c00 },
+    & ifmt_lda_disp, { 0xc8003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2449,7 +1833,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_offset, { 0x98000000 },
+    & ifmt_lda_offset, { 0x98000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2458,7 +1842,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_indirect_offset, { 0x98002000 },
+    & ifmt_lda_offset, { 0x98002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2467,7 +1851,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_indirect, { 0x98001000 },
+    & ifmt_lda_indirect, { 0x98001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2476,7 +1860,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_indirect_index, { 0x98001c00 },
+    & ifmt_lda_indirect, { 0x98001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2485,7 +1869,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_DISP, "ldl-disp", "ldl",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_disp, { 0x98003000 },
+    & ifmt_lda_disp, { 0x98003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2494,7 +1878,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_indirect_disp, { 0x98003400 },
+    & ifmt_lda_disp, { 0x98003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2503,7 +1887,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_index_disp, { 0x98003800 },
+    & ifmt_lda_disp, { 0x98003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2512,7 +1896,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldl_indirect_index_disp, { 0x98003c00 },
+    & ifmt_lda_disp, { 0x98003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2521,7 +1905,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_offset, { 0xa0000000 },
+    & ifmt_lda_offset, { 0xa0000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2530,7 +1914,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_indirect_offset, { 0xa0002000 },
+    & ifmt_lda_offset, { 0xa0002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2539,7 +1923,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_indirect, { 0xa0001000 },
+    & ifmt_lda_indirect, { 0xa0001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2548,7 +1932,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_indirect_index, { 0xa0001c00 },
+    & ifmt_lda_indirect, { 0xa0001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2557,7 +1941,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_DISP, "ldt-disp", "ldt",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_disp, { 0xa0003000 },
+    & ifmt_lda_disp, { 0xa0003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2566,7 +1950,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_indirect_disp, { 0xa0003400 },
+    & ifmt_lda_disp, { 0xa0003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2575,7 +1959,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_index_disp, { 0xa0003800 },
+    & ifmt_lda_disp, { 0xa0003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2584,7 +1968,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldt_indirect_index_disp, { 0xa0003c00 },
+    & ifmt_lda_disp, { 0xa0003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2593,7 +1977,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_offset, { 0xb0000000 },
+    & ifmt_lda_offset, { 0xb0000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2602,7 +1986,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_indirect_offset, { 0xb0002000 },
+    & ifmt_lda_offset, { 0xb0002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2611,7 +1995,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_indirect, { 0xb0001000 },
+    & ifmt_lda_indirect, { 0xb0001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2620,7 +2004,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_indirect_index, { 0xb0001c00 },
+    & ifmt_lda_indirect, { 0xb0001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2629,7 +2013,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_disp, { 0xb0003000 },
+    & ifmt_lda_disp, { 0xb0003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2638,7 +2022,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_indirect_disp, { 0xb0003400 },
+    & ifmt_lda_disp, { 0xb0003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2647,7 +2031,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_index_disp, { 0xb0003800 },
+    & ifmt_lda_disp, { 0xb0003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2656,7 +2040,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
-    & fmt_ldq_indirect_index_disp, { 0xb0003c00 },
+    & ifmt_lda_disp, { 0xb0003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2665,7 +2049,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_OFFSET, "st-offset", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
-    & fmt_st_offset, { 0x92000000 },
+    & ifmt_st_offset, { 0x92000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2674,7 +2058,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_st_indirect_offset, { 0x92002000 },
+    & ifmt_st_offset, { 0x92002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2683,7 +2067,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_INDIRECT, "st-indirect", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_st_indirect, { 0x92001000 },
+    & ifmt_st_indirect, { 0x92001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2692,7 +2076,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_st_indirect_index, { 0x92001c00 },
+    & ifmt_st_indirect, { 0x92001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2701,7 +2085,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_DISP, "st-disp", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
-    & fmt_st_disp, { 0x92003000 },
+    & ifmt_st_disp, { 0x92003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2710,7 +2094,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_st_indirect_disp, { 0x92003400 },
+    & ifmt_st_disp, { 0x92003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2719,7 +2103,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
-    & fmt_st_index_disp, { 0x92003800 },
+    & ifmt_st_disp, { 0x92003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2728,7 +2112,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_st_indirect_index_disp, { 0x92003c00 },
+    & ifmt_st_disp, { 0x92003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2737,7 +2121,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_OFFSET, "stob-offset", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
-    & fmt_stob_offset, { 0x82000000 },
+    & ifmt_st_offset, { 0x82000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2746,7 +2130,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_stob_indirect_offset, { 0x82002000 },
+    & ifmt_st_offset, { 0x82002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2755,7 +2139,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_stob_indirect, { 0x82001000 },
+    & ifmt_st_indirect, { 0x82001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2764,7 +2148,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stob_indirect_index, { 0x82001c00 },
+    & ifmt_st_indirect, { 0x82001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2773,7 +2157,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_DISP, "stob-disp", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
-    & fmt_stob_disp, { 0x82003000 },
+    & ifmt_st_disp, { 0x82003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2782,7 +2166,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_stob_indirect_disp, { 0x82003400 },
+    & ifmt_st_disp, { 0x82003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2791,7 +2175,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
-    & fmt_stob_index_disp, { 0x82003800 },
+    & ifmt_st_disp, { 0x82003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2800,7 +2184,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stob_indirect_index_disp, { 0x82003c00 },
+    & ifmt_st_disp, { 0x82003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2809,7 +2193,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_OFFSET, "stos-offset", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
-    & fmt_stos_offset, { 0x8a000000 },
+    & ifmt_st_offset, { 0x8a000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2818,7 +2202,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_stos_indirect_offset, { 0x8a002000 },
+    & ifmt_st_offset, { 0x8a002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2827,7 +2211,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_stos_indirect, { 0x8a001000 },
+    & ifmt_st_indirect, { 0x8a001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2836,7 +2220,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stos_indirect_index, { 0x8a001c00 },
+    & ifmt_st_indirect, { 0x8a001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2845,7 +2229,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_DISP, "stos-disp", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
-    & fmt_stos_disp, { 0x8a003000 },
+    & ifmt_st_disp, { 0x8a003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2854,7 +2238,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_stos_indirect_disp, { 0x8a003400 },
+    & ifmt_st_disp, { 0x8a003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2863,7 +2247,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
-    & fmt_stos_index_disp, { 0x8a003800 },
+    & ifmt_st_disp, { 0x8a003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2872,7 +2256,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stos_indirect_index_disp, { 0x8a003c00 },
+    & ifmt_st_disp, { 0x8a003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2881,7 +2265,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_OFFSET, "stl-offset", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
-    & fmt_stl_offset, { 0x9a000000 },
+    & ifmt_st_offset, { 0x9a000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2890,7 +2274,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_stl_indirect_offset, { 0x9a002000 },
+    & ifmt_st_offset, { 0x9a002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2899,7 +2283,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_stl_indirect, { 0x9a001000 },
+    & ifmt_st_indirect, { 0x9a001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2908,7 +2292,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stl_indirect_index, { 0x9a001c00 },
+    & ifmt_st_indirect, { 0x9a001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2917,7 +2301,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_DISP, "stl-disp", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
-    & fmt_stl_disp, { 0x9a003000 },
+    & ifmt_st_disp, { 0x9a003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2926,7 +2310,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_stl_indirect_disp, { 0x9a003400 },
+    & ifmt_st_disp, { 0x9a003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2935,7 +2319,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
-    & fmt_stl_index_disp, { 0x9a003800 },
+    & ifmt_st_disp, { 0x9a003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2944,7 +2328,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stl_indirect_index_disp, { 0x9a003c00 },
+    & ifmt_st_disp, { 0x9a003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2953,7 +2337,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_OFFSET, "stt-offset", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
-    & fmt_stt_offset, { 0xa2000000 },
+    & ifmt_st_offset, { 0xa2000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2962,7 +2346,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_stt_indirect_offset, { 0xa2002000 },
+    & ifmt_st_offset, { 0xa2002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2971,7 +2355,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_stt_indirect, { 0xa2001000 },
+    & ifmt_st_indirect, { 0xa2001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2980,7 +2364,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stt_indirect_index, { 0xa2001c00 },
+    & ifmt_st_indirect, { 0xa2001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2989,7 +2373,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_DISP, "stt-disp", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
-    & fmt_stt_disp, { 0xa2003000 },
+    & ifmt_st_disp, { 0xa2003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -2998,7 +2382,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_stt_indirect_disp, { 0xa2003400 },
+    & ifmt_st_disp, { 0xa2003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3007,7 +2391,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
-    & fmt_stt_index_disp, { 0xa2003800 },
+    & ifmt_st_disp, { 0xa2003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3016,7 +2400,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stt_indirect_index_disp, { 0xa2003c00 },
+    & ifmt_st_disp, { 0xa2003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3025,7 +2409,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_OFFSET, "stq-offset", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
-    & fmt_stq_offset, { 0xb2000000 },
+    & ifmt_st_offset, { 0xb2000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3034,7 +2418,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_stq_indirect_offset, { 0xb2002000 },
+    & ifmt_st_offset, { 0xb2002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3043,7 +2427,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_stq_indirect, { 0xb2001000 },
+    & ifmt_st_indirect, { 0xb2001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3052,7 +2436,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stq_indirect_index, { 0xb2001c00 },
+    & ifmt_st_indirect, { 0xb2001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3061,7 +2445,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_DISP, "stq-disp", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
-    & fmt_stq_disp, { 0xb2003000 },
+    & ifmt_st_disp, { 0xb2003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3070,7 +2454,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_stq_indirect_disp, { 0xb2003400 },
+    & ifmt_st_disp, { 0xb2003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3079,7 +2463,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
-    & fmt_stq_index_disp, { 0xb2003800 },
+    & ifmt_st_disp, { 0xb2003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3088,7 +2472,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_stq_indirect_index_disp, { 0xb2003c00 },
+    & ifmt_st_disp, { 0xb2003c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3097,7 +2481,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x32000000 },
+    & ifmt_cmpobe_reg, { 0x32000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3106,7 +2490,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x32002000 },
+    & ifmt_cmpobe_lit, { 0x32002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3115,7 +2499,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x35000000 },
+    & ifmt_cmpobe_reg, { 0x35000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3124,7 +2508,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x35002000 },
+    & ifmt_cmpobe_lit, { 0x35002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3133,7 +2517,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_reg, { 0x34000000 },
+    & ifmt_cmpobe_reg, { 0x34000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3142,7 +2526,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_lit, { 0x34002000 },
+    & ifmt_cmpobe_lit, { 0x34002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3151,7 +2535,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_reg, { 0x36000000 },
+    & ifmt_cmpobe_reg, { 0x36000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3160,7 +2544,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_lit, { 0x36002000 },
+    & ifmt_cmpobe_lit, { 0x36002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3169,7 +2553,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_reg, { 0x31000000 },
+    & ifmt_cmpobe_reg, { 0x31000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3178,7 +2562,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_lit, { 0x31002000 },
+    & ifmt_cmpobe_lit, { 0x31002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3187,7 +2571,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_reg, { 0x33000000 },
+    & ifmt_cmpobe_reg, { 0x33000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3196,7 +2580,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobl_lit, { 0x33002000 },
+    & ifmt_cmpobe_lit, { 0x33002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3205,7 +2589,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x3a000000 },
+    & ifmt_cmpobe_reg, { 0x3a000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3214,7 +2598,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x3a002000 },
+    & ifmt_cmpobe_lit, { 0x3a002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3223,7 +2607,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x3d000000 },
+    & ifmt_cmpobe_reg, { 0x3d000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3232,7 +2616,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x3d002000 },
+    & ifmt_cmpobe_lit, { 0x3d002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3241,7 +2625,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x3c000000 },
+    & ifmt_cmpobe_reg, { 0x3c000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3250,7 +2634,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x3c002000 },
+    & ifmt_cmpobe_lit, { 0x3c002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3259,7 +2643,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x3e000000 },
+    & ifmt_cmpobe_reg, { 0x3e000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3268,7 +2652,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x3e002000 },
+    & ifmt_cmpobe_lit, { 0x3e002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3277,7 +2661,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x39000000 },
+    & ifmt_cmpobe_reg, { 0x39000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3286,7 +2670,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x39002000 },
+    & ifmt_cmpobe_lit, { 0x39002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3295,7 +2679,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x3b000000 },
+    & ifmt_cmpobe_reg, { 0x3b000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3304,7 +2688,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_lit, { 0x3b002000 },
+    & ifmt_cmpobe_lit, { 0x3b002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3313,7 +2697,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BBC_REG, "bbc-reg", "bbc",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x30000000 },
+    & ifmt_cmpobe_reg, { 0x30000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3322,7 +2706,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BBC_LIT, "bbc-lit", "bbc",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_bbc_lit, { 0x30002000 },
+    & ifmt_cmpobe_lit, { 0x30002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3331,7 +2715,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BBS_REG, "bbs-reg", "bbs",
     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_cmpobe_reg, { 0x37000000 },
+    & ifmt_cmpobe_reg, { 0x37000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3340,7 +2724,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BBS_LIT, "bbs-lit", "bbs",
     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
-    & fmt_bbc_lit, { 0x37002000 },
+    & ifmt_cmpobe_lit, { 0x37002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3349,7 +2733,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPI, "cmpi", "cmpi",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
-    & fmt_cmpi, { 0x5a002080 },
+    & ifmt_mulo, { 0x5a002080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3358,7 +2742,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPI1, "cmpi1", "cmpi",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
-    & fmt_cmpi1, { 0x5a002880 },
+    & ifmt_mulo1, { 0x5a002880 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3367,7 +2751,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPI2, "cmpi2", "cmpi",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
-    & fmt_cmpi2, { 0x5a003080 },
+    & ifmt_mulo2, { 0x5a003080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3376,7 +2760,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPI3, "cmpi3", "cmpi",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
-    & fmt_cmpi3, { 0x5a003880 },
+    & ifmt_mulo3, { 0x5a003880 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3385,7 +2769,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPO, "cmpo", "cmpo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
-    & fmt_cmpi, { 0x5a002000 },
+    & ifmt_mulo, { 0x5a002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3394,7 +2778,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPO1, "cmpo1", "cmpo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
-    & fmt_cmpi1, { 0x5a002800 },
+    & ifmt_mulo1, { 0x5a002800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3403,7 +2787,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPO2, "cmpo2", "cmpo",
     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
-    & fmt_cmpi2, { 0x5a003000 },
+    & ifmt_mulo2, { 0x5a003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3412,7 +2796,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CMPO3, "cmpo3", "cmpo",
     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
-    & fmt_cmpi3, { 0x5a003800 },
+    & ifmt_mulo3, { 0x5a003800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3421,7 +2805,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTNO_REG, "testno-reg", "testno",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x20000000 },
+    & ifmt_cmpobe_reg, { 0x20000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3430,7 +2814,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTG_REG, "testg-reg", "testg",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x21000000 },
+    & ifmt_cmpobe_reg, { 0x21000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3439,7 +2823,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTE_REG, "teste-reg", "teste",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x22000000 },
+    & ifmt_cmpobe_reg, { 0x22000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3448,7 +2832,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTGE_REG, "testge-reg", "testge",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x23000000 },
+    & ifmt_cmpobe_reg, { 0x23000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3457,7 +2841,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTL_REG, "testl-reg", "testl",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x24000000 },
+    & ifmt_cmpobe_reg, { 0x24000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3466,7 +2850,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTNE_REG, "testne-reg", "testne",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x25000000 },
+    & ifmt_cmpobe_reg, { 0x25000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3475,7 +2859,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTLE_REG, "testle-reg", "testle",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x26000000 },
+    & ifmt_cmpobe_reg, { 0x26000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3484,7 +2868,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_TESTO_REG, "testo-reg", "testo",
     { { MNEM, ' ', OP (BR_SRC1), 0 } },
-    & fmt_testno_reg, { 0x27000000 },
+    & ifmt_cmpobe_reg, { 0x27000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
@@ -3493,7 +2877,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BNO, "bno", "bno",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x10000000 },
+    & ifmt_bno, { 0x10000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3502,7 +2886,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BG, "bg", "bg",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x11000000 },
+    & ifmt_bno, { 0x11000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3511,7 +2895,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BE, "be", "be",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x12000000 },
+    & ifmt_bno, { 0x12000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3520,7 +2904,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BGE, "bge", "bge",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x13000000 },
+    & ifmt_bno, { 0x13000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3529,7 +2913,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BL, "bl", "bl",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x14000000 },
+    & ifmt_bno, { 0x14000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3538,7 +2922,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BNE, "bne", "bne",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x15000000 },
+    & ifmt_bno, { 0x15000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3547,7 +2931,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BLE, "ble", "ble",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x16000000 },
+    & ifmt_bno, { 0x16000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3556,7 +2940,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BO, "bo", "bo",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_bno, { 0x17000000 },
+    & ifmt_bno, { 0x17000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3565,7 +2949,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_B, "b", "b",
     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
-    & fmt_b, { 0x8000000 },
+    & ifmt_bno, { 0x8000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3574,7 +2958,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_bx_indirect_offset, { 0x84002000 },
+    & ifmt_lda_offset, { 0x84002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3583,7 +2967,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
     { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_bx_indirect, { 0x84001000 },
+    & ifmt_lda_indirect, { 0x84001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3592,7 +2976,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
-    & fmt_bx_indirect_index, { 0x84001c00 },
+    & ifmt_lda_indirect, { 0x84001c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3601,7 +2985,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BX_DISP, "bx-disp", "bx",
     { { MNEM, ' ', OP (OPTDISP), 0 } },
-    & fmt_bx_disp, { 0x84003000 },
+    & ifmt_lda_disp, { 0x84003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3610,7 +2994,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
-    & fmt_bx_indirect_disp, { 0x84003400 },
+    & ifmt_lda_disp, { 0x84003400 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3619,7 +3003,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CALLX_DISP, "callx-disp", "callx",
     { { MNEM, ' ', OP (OPTDISP), 0 } },
-    & fmt_callx_disp, { 0x86003000 },
+    & ifmt_lda_disp, { 0x86003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3628,7 +3012,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
     { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
-    & fmt_callx_indirect, { 0x86001000 },
+    & ifmt_lda_indirect, { 0x86001000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3637,7 +3021,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
-    & fmt_callx_indirect_offset, { 0x86002000 },
+    & ifmt_lda_offset, { 0x86002000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3646,7 +3030,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_RET, "ret", "ret",
     { { MNEM, 0 } },
-    & fmt_ret, { 0xa000000 },
+    & ifmt_bno, { 0xa000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3655,7 +3039,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_CALLS, "calls", "calls",
     { { MNEM, ' ', OP (SRC1), 0 } },
-    & fmt_calls, { 0x66003000 },
+    & ifmt_mulo, { 0x66003000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3664,7 +3048,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_FMARK, "fmark", "fmark",
     { { MNEM, 0 } },
-    & fmt_fmark, { 0x66003e00 },
+    & ifmt_mulo, { 0x66003e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
@@ -3673,7 +3057,7 @@ const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     I960_INSN_FLUSHREG, "flushreg", "flushreg",
     { { MNEM, 0 } },
-    & fmt_flushreg, { 0x66003e80 },
+    & ifmt_mulo, { 0x66003e80 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
   },
diff --git a/opcodes/i960c-opc.h b/opcodes/i960c-opc.h
index 7d11e87..b526f41 100644
--- a/opcodes/i960c-opc.h
+++ b/opcodes/i960c-opc.h
@@ -290,7 +290,7 @@ typedef enum cgen_operand_type {
 #define MAX_OPERANDS ((int) I960_OPERAND_MAX)
 
 /* Maximum number of operands referenced by any insn.  */
-#define MAX_OPERAND_INSTANCES 54
+#define MAX_OPERAND_INSTANCES 8
 
 /* Insn attribute indices.  */
 
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 394d683..e9c1f74 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -3,7 +3,7 @@
 
 THIS FILE IS USED TO GENERATE m32r-opc.c.
 
-Copyright (C) 1998 Free Software Foundation, Inc.
+Copyright (C) 1998, 1999 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and GDB, the GNU debugger.
 
@@ -558,8 +558,8 @@ static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
@@ -588,25 +588,25 @@ static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
-  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
-  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
+  { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
-  { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
-  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
@@ -625,31 +625,31 @@ static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
+  { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
-  { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
-  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
-  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { 0 }
@@ -658,8 +658,8 @@ static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
 /* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
-  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { 0 }
@@ -669,8 +669,8 @@ static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
 /* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
-  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
   { 0 }
@@ -697,13 +697,22 @@ static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
   { 0 }
 };
 
 /* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_cmpeq_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+  { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
@@ -712,12 +721,21 @@ static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
 
 /* end-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
+  { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+  { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
+  { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_divh_ops[] = {
   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
   { 0 }
 };
 
+/* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
@@ -742,53 +760,53 @@ static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
-  { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
   { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
-  { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
   { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
-  { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
   { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { 0 }
@@ -813,10 +831,10 @@ static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
-  { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+  { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
   { 0 }
 };
 
@@ -911,21 +929,21 @@ static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
 /* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
   { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
-  { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0, 0 },
+  { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_INT, & OP_ENT (IMM1), 0, 0 },
   { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0, 0 },
   { 0 }
 };
 
 /* end-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
-  { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
-  { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
-  { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
   { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
-  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+  { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
+  { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
+  { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
   { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
-  { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { 0 }
 };
 
@@ -936,82 +954,82 @@ static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
-  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
+  { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
-  { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0, 0 },
+  { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_INT, & OP_ENT (UIMM5), 0, 0 },
   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
   { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
-  { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
-  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+  { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
   { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
-  { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0, 0 },
-  { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
-  { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0, 0 },
   { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
+  { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
   { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
   { 0 }
@@ -1019,10 +1037,10 @@ static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
 
 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
   { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
-  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF },
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, COND_REF },
-  { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF },
   { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
   { 0 }
 };
 
@@ -1045,8 +1063,8 @@ static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
-  { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
   { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
+  { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
   { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
   { 0 }
 };
@@ -1063,6 +1081,16 @@ static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_msblo_ops[] = {
+  { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
+  { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
@@ -1086,312 +1114,178 @@ static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
 
 #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
 
-static const CGEN_IFMT fmt_empty = {
+static const CGEN_IFMT ifmt_empty = {
   0, 0, 0x0, { 0 }
 };
 
-static const CGEN_IFMT fmt_add = {
+static const CGEN_IFMT ifmt_add = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_add3 = {
+static const CGEN_IFMT ifmt_add3 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_and3 = {
+static const CGEN_IFMT ifmt_and3 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_or3 = {
+static const CGEN_IFMT ifmt_or3 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_addi = {
+static const CGEN_IFMT ifmt_addi = {
   16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
 };
 
-static const CGEN_IFMT fmt_addv = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_addv3 = {
+static const CGEN_IFMT ifmt_addv3 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_addx = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_bc8 = {
+static const CGEN_IFMT ifmt_bc8 = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
-static const CGEN_IFMT fmt_bc24 = {
+static const CGEN_IFMT ifmt_bc24 = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
-static const CGEN_IFMT fmt_beq = {
+static const CGEN_IFMT ifmt_beq = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
 };
 
-static const CGEN_IFMT fmt_beqz = {
+static const CGEN_IFMT ifmt_beqz = {
   32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
 };
 
-static const CGEN_IFMT fmt_bl8 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
-};
-
-static const CGEN_IFMT fmt_bl24 = {
-  32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
-};
-
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_bcl8 = {
+static const CGEN_IFMT ifmt_bcl8 = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_bcl24 = {
+static const CGEN_IFMT ifmt_bcl24 = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_bra8 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+static const CGEN_IFMT ifmt_cmp = {
+  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_bra24 = {
-  32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+static const CGEN_IFMT ifmt_cmpi = {
+  32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_cmp = {
+/* start-sanitize-m32rx */
+static const CGEN_IFMT ifmt_cmpeq = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_cmpi = {
-  32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
+/* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_cmpz = {
+static const CGEN_IFMT ifmt_cmpz = {
   16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_div = {
+static const CGEN_IFMT ifmt_div = {
   32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_jc = {
-  16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+static const CGEN_IFMT ifmt_divh = {
+  32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_jl = {
+/* start-sanitize-m32rx */
+static const CGEN_IFMT ifmt_jc = {
   16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_jmp = {
+/* end-sanitize-m32rx */
+static const CGEN_IFMT ifmt_jl = {
   16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_ld = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_d = {
-  32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
-static const CGEN_IFMT fmt_ldb = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_ldb_d = {
-  32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
-static const CGEN_IFMT fmt_ldh = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_ldh_d = {
-  32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
-static const CGEN_IFMT fmt_ld_plus = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_ld24 = {
+static const CGEN_IFMT ifmt_ld24 = {
   32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 }
 };
 
-static const CGEN_IFMT fmt_ldi8 = {
-  16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
-};
-
-static const CGEN_IFMT fmt_ldi16 = {
+static const CGEN_IFMT ifmt_ldi16 = {
   32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_lock = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_machi = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_machi_a = {
+static const CGEN_IFMT ifmt_machi_a = {
   16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_mulhi = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-/* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_mulhi_a = {
-  16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
-};
-
-/* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_mv = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_mvfachi = {
+static const CGEN_IFMT ifmt_mvfachi = {
   16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_mvfachi_a = {
+static const CGEN_IFMT ifmt_mvfachi_a = {
   16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_mvfc = {
+static const CGEN_IFMT ifmt_mvfc = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_mvtachi = {
+static const CGEN_IFMT ifmt_mvtachi = {
   16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_mvtachi_a = {
+static const CGEN_IFMT ifmt_mvtachi_a = {
   16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_mvtc = {
+static const CGEN_IFMT ifmt_mvtc = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_nop = {
-  16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_rac = {
+static const CGEN_IFMT ifmt_nop = {
   16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_rac_dsi = {
+static const CGEN_IFMT ifmt_rac_dsi = {
   16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_rte = {
-  16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_seth = {
+static const CGEN_IFMT ifmt_seth = {
   32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 }
 };
 
-static const CGEN_IFMT fmt_sll3 = {
-  32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
-static const CGEN_IFMT fmt_slli = {
+static const CGEN_IFMT ifmt_slli = {
   16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 }
 };
 
-static const CGEN_IFMT fmt_st = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_st_d = {
-  32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
-static const CGEN_IFMT fmt_stb = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_stb_d = {
-  32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
-};
-
-static const CGEN_IFMT fmt_sth = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_sth_d = {
+static const CGEN_IFMT ifmt_st_d = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_st_plus = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-static const CGEN_IFMT fmt_trap = {
+static const CGEN_IFMT ifmt_trap = {
   16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 }
 };
 
-static const CGEN_IFMT fmt_unlock = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_satb = {
+static const CGEN_IFMT ifmt_satb = {
   32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_sat = {
-  32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
-};
-
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_sadd = {
-  16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_macwu1 = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_mulwu1 = {
-  16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
-};
-
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_sc = {
+static const CGEN_IFMT ifmt_sadd = {
   16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
@@ -1417,7 +1311,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ADD, "add", "add",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0xa0 },
+    & ifmt_add, { 0xa0 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1426,7 +1320,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ADD3, "add3", "add3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
-    & fmt_add3, { 0x80a00000 },
+    & ifmt_add3, { 0x80a00000 },
     (PTR) & fmt_add3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1435,7 +1329,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_AND, "and", "and",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0xc0 },
+    & ifmt_add, { 0xc0 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1444,7 +1338,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_AND3, "and3", "and3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
-    & fmt_and3, { 0x80c00000 },
+    & ifmt_and3, { 0x80c00000 },
     (PTR) & fmt_and3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1453,7 +1347,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_OR, "or", "or",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0xe0 },
+    & ifmt_add, { 0xe0 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1462,7 +1356,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_OR3, "or3", "or3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
-    & fmt_or3, { 0x80e00000 },
+    & ifmt_or3, { 0x80e00000 },
     (PTR) & fmt_or3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1471,7 +1365,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_XOR, "xor", "xor",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0xd0 },
+    & ifmt_add, { 0xd0 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1480,7 +1374,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_XOR3, "xor3", "xor3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
-    & fmt_and3, { 0x80d00000 },
+    & ifmt_and3, { 0x80d00000 },
     (PTR) & fmt_and3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1489,7 +1383,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ADDI, "addi", "addi",
     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
-    & fmt_addi, { 0x4000 },
+    & ifmt_addi, { 0x4000 },
     (PTR) & fmt_addi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1498,7 +1392,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ADDV, "addv", "addv",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_addv, { 0x80 },
+    & ifmt_add, { 0x80 },
     (PTR) & fmt_addv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1507,7 +1401,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ADDV3, "addv3", "addv3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
-    & fmt_addv3, { 0x80800000 },
+    & ifmt_addv3, { 0x80800000 },
     (PTR) & fmt_addv3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1516,7 +1410,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ADDX, "addx", "addx",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_addx, { 0x90 },
+    & ifmt_add, { 0x90 },
     (PTR) & fmt_addx_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1525,7 +1419,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BC8, "bc8", "bc.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bc8, { 0x7c00 },
+    & ifmt_bc8, { 0x7c00 },
     (PTR) & fmt_bc8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1534,7 +1428,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BC24, "bc24", "bc.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bc24, { 0xfc000000 },
+    & ifmt_bc24, { 0xfc000000 },
     (PTR) & fmt_bc24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1543,7 +1437,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BEQ, "beq", "beq",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beq, { 0xb0000000 },
+    & ifmt_beq, { 0xb0000000 },
     (PTR) & fmt_beq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1552,7 +1446,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BEQZ, "beqz", "beqz",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beqz, { 0xb0800000 },
+    & ifmt_beqz, { 0xb0800000 },
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1561,7 +1455,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BGEZ, "bgez", "bgez",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beqz, { 0xb0b00000 },
+    & ifmt_beqz, { 0xb0b00000 },
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1570,7 +1464,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BGTZ, "bgtz", "bgtz",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beqz, { 0xb0d00000 },
+    & ifmt_beqz, { 0xb0d00000 },
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1579,7 +1473,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BLEZ, "blez", "blez",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beqz, { 0xb0c00000 },
+    & ifmt_beqz, { 0xb0c00000 },
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1588,7 +1482,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BLTZ, "bltz", "bltz",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beqz, { 0xb0a00000 },
+    & ifmt_beqz, { 0xb0a00000 },
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1597,7 +1491,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BNEZ, "bnez", "bnez",
     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beqz, { 0xb0900000 },
+    & ifmt_beqz, { 0xb0900000 },
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1606,7 +1500,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BL8, "bl8", "bl.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bl8, { 0x7e00 },
+    & ifmt_bc8, { 0x7e00 },
     (PTR) & fmt_bl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1615,7 +1509,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BL24, "bl24", "bl.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bl24, { 0xfe000000 },
+    & ifmt_bc24, { 0xfe000000 },
     (PTR) & fmt_bl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1625,7 +1519,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BCL8, "bcl8", "bcl.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bcl8, { 0x7800 },
+    & ifmt_bcl8, { 0x7800 },
     (PTR) & fmt_bcl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1636,7 +1530,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BCL24, "bcl24", "bcl.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bcl24, { 0xf8000000 },
+    & ifmt_bcl24, { 0xf8000000 },
     (PTR) & fmt_bcl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -1646,7 +1540,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BNC8, "bnc8", "bnc.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bc8, { 0x7d00 },
+    & ifmt_bc8, { 0x7d00 },
     (PTR) & fmt_bc8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1655,7 +1549,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BNC24, "bnc24", "bnc.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bc24, { 0xfd000000 },
+    & ifmt_bc24, { 0xfd000000 },
     (PTR) & fmt_bc24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1664,7 +1558,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BNE, "bne", "bne",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
-    & fmt_beq, { 0xb0100000 },
+    & ifmt_beq, { 0xb0100000 },
     (PTR) & fmt_beq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1673,7 +1567,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BRA8, "bra8", "bra.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bra8, { 0x7f00 },
+    & ifmt_bc8, { 0x7f00 },
     (PTR) & fmt_bra8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1682,7 +1576,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BRA24, "bra24", "bra.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bra24, { 0xff000000 },
+    & ifmt_bc24, { 0xff000000 },
     (PTR) & fmt_bra24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1692,7 +1586,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BNCL8, "bncl8", "bncl.s",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bcl8, { 0x7900 },
+    & ifmt_bcl8, { 0x7900 },
     (PTR) & fmt_bcl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1703,7 +1597,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_BNCL24, "bncl24", "bncl.l",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bcl24, { 0xf9000000 },
+    & ifmt_bcl24, { 0xf9000000 },
     (PTR) & fmt_bcl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -1713,7 +1607,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_CMP, "cmp", "cmp",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_cmp, { 0x40 },
+    & ifmt_cmp, { 0x40 },
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1722,7 +1616,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_CMPI, "cmpi", "cmpi",
     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
-    & fmt_cmpi, { 0x80400000 },
+    & ifmt_cmpi, { 0x80400000 },
     (PTR) & fmt_cmpi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1731,7 +1625,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_CMPU, "cmpu", "cmpu",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_cmp, { 0x50 },
+    & ifmt_cmp, { 0x50 },
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1740,7 +1634,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_CMPUI, "cmpui", "cmpui",
     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
-    & fmt_cmpi, { 0x80500000 },
+    & ifmt_cmpi, { 0x80500000 },
     (PTR) & fmt_cmpi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1750,8 +1644,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_cmp, { 0x60 },
-    (PTR) & fmt_cmp_ops[0],
+    & ifmt_cmpeq, { 0x60 },
+    (PTR) & fmt_cmpeq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
@@ -1761,7 +1655,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_CMPZ, "cmpz", "cmpz",
     { { MNEM, ' ', OP (SRC2), 0 } },
-    & fmt_cmpz, { 0x70 },
+    & ifmt_cmpz, { 0x70 },
     (PTR) & fmt_cmpz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
@@ -1771,7 +1665,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_DIV, "div", "div",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_div, { 0x90000000 },
+    & ifmt_div, { 0x90000000 },
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1780,7 +1674,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_DIVU, "divu", "divu",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_div, { 0x90100000 },
+    & ifmt_div, { 0x90100000 },
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1789,7 +1683,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_REM, "rem", "rem",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_div, { 0x90200000 },
+    & ifmt_div, { 0x90200000 },
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1798,7 +1692,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_REMU, "remu", "remu",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_div, { 0x90300000 },
+    & ifmt_div, { 0x90300000 },
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1808,8 +1702,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_DIVH, "divh", "divh",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_div, { 0x90000010 },
-    (PTR) & fmt_div_ops[0],
+    & ifmt_divh, { 0x90000010 },
+    (PTR) & fmt_divh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
@@ -1819,7 +1713,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_JC, "jc", "jc",
     { { MNEM, ' ', OP (SR), 0 } },
-    & fmt_jc, { 0x1cc0 },
+    & ifmt_jc, { 0x1cc0 },
     (PTR) & fmt_jc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1830,7 +1724,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_JNC, "jnc", "jnc",
     { { MNEM, ' ', OP (SR), 0 } },
-    & fmt_jc, { 0x1dc0 },
+    & ifmt_jc, { 0x1dc0 },
     (PTR) & fmt_jc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -1840,7 +1734,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_JL, "jl", "jl",
     { { MNEM, ' ', OP (SR), 0 } },
-    & fmt_jl, { 0x1ec0 },
+    & ifmt_jl, { 0x1ec0 },
     (PTR) & fmt_jl_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1849,7 +1743,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_JMP, "jmp", "jmp",
     { { MNEM, ' ', OP (SR), 0 } },
-    & fmt_jmp, { 0x1fc0 },
+    & ifmt_jl, { 0x1fc0 },
     (PTR) & fmt_jmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1858,7 +1752,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LD, "ld", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
-    & fmt_ld, { 0x20c0 },
+    & ifmt_add, { 0x20c0 },
     (PTR) & fmt_ld_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1867,7 +1761,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LD_D, "ld-d", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
-    & fmt_ld_d, { 0xa0c00000 },
+    & ifmt_add3, { 0xa0c00000 },
     (PTR) & fmt_ld_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1876,7 +1770,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDB, "ldb", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
-    & fmt_ldb, { 0x2080 },
+    & ifmt_add, { 0x2080 },
     (PTR) & fmt_ldb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1885,7 +1779,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDB_D, "ldb-d", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
-    & fmt_ldb_d, { 0xa0800000 },
+    & ifmt_add3, { 0xa0800000 },
     (PTR) & fmt_ldb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1894,7 +1788,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDH, "ldh", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
-    & fmt_ldh, { 0x20a0 },
+    & ifmt_add, { 0x20a0 },
     (PTR) & fmt_ldh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1903,7 +1797,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDH_D, "ldh-d", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
-    & fmt_ldh_d, { 0xa0a00000 },
+    & ifmt_add3, { 0xa0a00000 },
     (PTR) & fmt_ldh_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1912,7 +1806,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDUB, "ldub", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
-    & fmt_ldb, { 0x2090 },
+    & ifmt_add, { 0x2090 },
     (PTR) & fmt_ldb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1921,7 +1815,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDUB_D, "ldub-d", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
-    & fmt_ldb_d, { 0xa0900000 },
+    & ifmt_add3, { 0xa0900000 },
     (PTR) & fmt_ldb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1930,7 +1824,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDUH, "lduh", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
-    & fmt_ldh, { 0x20b0 },
+    & ifmt_add, { 0x20b0 },
     (PTR) & fmt_ldh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1939,7 +1833,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDUH_D, "lduh-d", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
-    & fmt_ldh_d, { 0xa0b00000 },
+    & ifmt_add3, { 0xa0b00000 },
     (PTR) & fmt_ldh_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1948,7 +1842,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LD_PLUS, "ld-plus", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
-    & fmt_ld_plus, { 0x20e0 },
+    & ifmt_add, { 0x20e0 },
     (PTR) & fmt_ld_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1957,7 +1851,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LD24, "ld24", "ld24",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
-    & fmt_ld24, { 0xe0000000 },
+    & ifmt_ld24, { 0xe0000000 },
     (PTR) & fmt_ld24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1966,7 +1860,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDI8, "ldi8", "ldi8",
     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
-    & fmt_ldi8, { 0x6000 },
+    & ifmt_addi, { 0x6000 },
     (PTR) & fmt_ldi8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -1975,7 +1869,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LDI16, "ldi16", "ldi16",
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
-    & fmt_ldi16, { 0x90f00000 },
+    & ifmt_ldi16, { 0x90f00000 },
     (PTR) & fmt_ldi16_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -1984,7 +1878,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_LOCK, "lock", "lock",
     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
-    & fmt_lock, { 0x20d0 },
+    & ifmt_add, { 0x20d0 },
     (PTR) & fmt_lock_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -1993,7 +1887,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACHI, "machi", "machi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_machi, { 0x3040 },
+    & ifmt_cmp, { 0x3040 },
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2003,7 +1897,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACHI_A, "machi-a", "machi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_machi_a, { 0x3040 },
+    & ifmt_machi_a, { 0x3040 },
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2013,7 +1907,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACLO, "maclo", "maclo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_machi, { 0x3050 },
+    & ifmt_cmp, { 0x3050 },
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2023,7 +1917,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACLO_A, "maclo-a", "maclo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_machi_a, { 0x3050 },
+    & ifmt_machi_a, { 0x3050 },
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2033,7 +1927,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACWHI, "macwhi", "macwhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_machi, { 0x3060 },
+    & ifmt_cmp, { 0x3060 },
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2043,7 +1937,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_machi_a, { 0x3060 },
+    & ifmt_machi_a, { 0x3060 },
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2053,7 +1947,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACWLO, "macwlo", "macwlo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_machi, { 0x3070 },
+    & ifmt_cmp, { 0x3070 },
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2063,7 +1957,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_machi_a, { 0x3070 },
+    & ifmt_machi_a, { 0x3070 },
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2073,7 +1967,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MUL, "mul", "mul",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0x1060 },
+    & ifmt_add, { 0x1060 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
   },
@@ -2082,7 +1976,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULHI, "mulhi", "mulhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_mulhi, { 0x3000 },
+    & ifmt_cmp, { 0x3000 },
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2092,7 +1986,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_mulhi_a, { 0x3000 },
+    & ifmt_machi_a, { 0x3000 },
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2102,7 +1996,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULLO, "mullo", "mullo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_mulhi, { 0x3010 },
+    & ifmt_cmp, { 0x3010 },
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2112,7 +2006,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULLO_A, "mullo-a", "mullo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_mulhi_a, { 0x3010 },
+    & ifmt_machi_a, { 0x3010 },
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2122,7 +2016,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_mulhi, { 0x3020 },
+    & ifmt_cmp, { 0x3020 },
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2132,7 +2026,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_mulhi_a, { 0x3020 },
+    & ifmt_machi_a, { 0x3020 },
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2142,7 +2036,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_mulhi, { 0x3030 },
+    & ifmt_cmp, { 0x3030 },
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2152,7 +2046,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
-    & fmt_mulhi_a, { 0x3030 },
+    & ifmt_machi_a, { 0x3030 },
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2162,7 +2056,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MV, "mv", "mv",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_mv, { 0x1080 },
+    & ifmt_add, { 0x1080 },
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2171,7 +2065,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
     { { MNEM, ' ', OP (DR), 0 } },
-    & fmt_mvfachi, { 0x50f0 },
+    & ifmt_mvfachi, { 0x50f0 },
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2181,7 +2075,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
-    & fmt_mvfachi_a, { 0x50f0 },
+    & ifmt_mvfachi_a, { 0x50f0 },
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2191,7 +2085,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
     { { MNEM, ' ', OP (DR), 0 } },
-    & fmt_mvfachi, { 0x50f1 },
+    & ifmt_mvfachi, { 0x50f1 },
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2201,7 +2095,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
-    & fmt_mvfachi_a, { 0x50f1 },
+    & ifmt_mvfachi_a, { 0x50f1 },
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2211,7 +2105,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
     { { MNEM, ' ', OP (DR), 0 } },
-    & fmt_mvfachi, { 0x50f2 },
+    & ifmt_mvfachi, { 0x50f2 },
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2221,7 +2115,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
-    & fmt_mvfachi_a, { 0x50f2 },
+    & ifmt_mvfachi_a, { 0x50f2 },
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2231,7 +2125,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVFC, "mvfc", "mvfc",
     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
-    & fmt_mvfc, { 0x1090 },
+    & ifmt_mvfc, { 0x1090 },
     (PTR) & fmt_mvfc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2240,7 +2134,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
     { { MNEM, ' ', OP (SRC1), 0 } },
-    & fmt_mvtachi, { 0x5070 },
+    & ifmt_mvtachi, { 0x5070 },
     (PTR) & fmt_mvtachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2250,7 +2144,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
-    & fmt_mvtachi_a, { 0x5070 },
+    & ifmt_mvtachi_a, { 0x5070 },
     (PTR) & fmt_mvtachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2260,7 +2154,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
     { { MNEM, ' ', OP (SRC1), 0 } },
-    & fmt_mvtachi, { 0x5071 },
+    & ifmt_mvtachi, { 0x5071 },
     (PTR) & fmt_mvtachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2270,7 +2164,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
-    & fmt_mvtachi_a, { 0x5071 },
+    & ifmt_mvtachi_a, { 0x5071 },
     (PTR) & fmt_mvtachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2280,7 +2174,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MVTC, "mvtc", "mvtc",
     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
-    & fmt_mvtc, { 0x10a0 },
+    & ifmt_mvtc, { 0x10a0 },
     (PTR) & fmt_mvtc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2289,7 +2183,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_NEG, "neg", "neg",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_mv, { 0x30 },
+    & ifmt_add, { 0x30 },
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2298,7 +2192,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_NOP, "nop", "nop",
     { { MNEM, 0 } },
-    & fmt_nop, { 0x7000 },
+    & ifmt_nop, { 0x7000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2307,7 +2201,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_NOT, "not", "not",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_mv, { 0xb0 },
+    & ifmt_add, { 0xb0 },
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2316,7 +2210,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_RAC, "rac", "rac",
     { { MNEM, 0 } },
-    & fmt_rac, { 0x5090 },
+    & ifmt_nop, { 0x5090 },
     (PTR) & fmt_rac_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2326,7 +2220,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
-    & fmt_rac_dsi, { 0x5090 },
+    & ifmt_rac_dsi, { 0x5090 },
     (PTR) & fmt_rac_dsi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2336,7 +2230,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_RACH, "rach", "rach",
     { { MNEM, 0 } },
-    & fmt_rac, { 0x5080 },
+    & ifmt_nop, { 0x5080 },
     (PTR) & fmt_rac_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
@@ -2346,7 +2240,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
-    & fmt_rac_dsi, { 0x5080 },
+    & ifmt_rac_dsi, { 0x5080 },
     (PTR) & fmt_rac_dsi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2356,7 +2250,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_RTE, "rte", "rte",
     { { MNEM, 0 } },
-    & fmt_rte, { 0x10d6 },
+    & ifmt_nop, { 0x10d6 },
     (PTR) & fmt_rte_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2365,7 +2259,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SETH, "seth", "seth",
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
-    & fmt_seth, { 0xd0c00000 },
+    & ifmt_seth, { 0xd0c00000 },
     (PTR) & fmt_seth_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2374,7 +2268,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SLL, "sll", "sll",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0x1040 },
+    & ifmt_add, { 0x1040 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2383,7 +2277,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SLL3, "sll3", "sll3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
-    & fmt_sll3, { 0x90c00000 },
+    & ifmt_addv3, { 0x90c00000 },
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2392,7 +2286,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SLLI, "slli", "slli",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
-    & fmt_slli, { 0x5040 },
+    & ifmt_slli, { 0x5040 },
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2401,7 +2295,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SRA, "sra", "sra",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0x1020 },
+    & ifmt_add, { 0x1020 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2410,7 +2304,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SRA3, "sra3", "sra3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
-    & fmt_sll3, { 0x90a00000 },
+    & ifmt_addv3, { 0x90a00000 },
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2419,7 +2313,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SRAI, "srai", "srai",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
-    & fmt_slli, { 0x5020 },
+    & ifmt_slli, { 0x5020 },
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2428,7 +2322,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SRL, "srl", "srl",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0x1000 },
+    & ifmt_add, { 0x1000 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2437,7 +2331,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SRL3, "srl3", "srl3",
     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
-    & fmt_sll3, { 0x90800000 },
+    & ifmt_addv3, { 0x90800000 },
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2446,7 +2340,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SRLI, "srli", "srli",
     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
-    & fmt_slli, { 0x5000 },
+    & ifmt_slli, { 0x5000 },
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2455,7 +2349,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ST, "st", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
-    & fmt_st, { 0x2040 },
+    & ifmt_cmp, { 0x2040 },
     (PTR) & fmt_st_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2464,7 +2358,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ST_D, "st-d", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
-    & fmt_st_d, { 0xa0400000 },
+    & ifmt_st_d, { 0xa0400000 },
     (PTR) & fmt_st_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2473,7 +2367,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_STB, "stb", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
-    & fmt_stb, { 0x2000 },
+    & ifmt_cmp, { 0x2000 },
     (PTR) & fmt_stb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2482,7 +2376,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_STB_D, "stb-d", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
-    & fmt_stb_d, { 0xa0000000 },
+    & ifmt_st_d, { 0xa0000000 },
     (PTR) & fmt_stb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2491,7 +2385,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_STH, "sth", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
-    & fmt_sth, { 0x2020 },
+    & ifmt_cmp, { 0x2020 },
     (PTR) & fmt_sth_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2500,7 +2394,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_STH_D, "sth-d", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
-    & fmt_sth_d, { 0xa0200000 },
+    & ifmt_st_d, { 0xa0200000 },
     (PTR) & fmt_sth_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2509,7 +2403,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ST_PLUS, "st-plus", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
-    & fmt_st_plus, { 0x2060 },
+    & ifmt_cmp, { 0x2060 },
     (PTR) & fmt_st_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2518,7 +2412,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_ST_MINUS, "st-minus", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
-    & fmt_st_plus, { 0x2070 },
+    & ifmt_cmp, { 0x2070 },
     (PTR) & fmt_st_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2527,7 +2421,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SUB, "sub", "sub",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_add, { 0x20 },
+    & ifmt_add, { 0x20 },
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2536,7 +2430,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SUBV, "subv", "subv",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_addv, { 0x0 },
+    & ifmt_add, { 0x0 },
     (PTR) & fmt_addv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2545,7 +2439,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SUBX, "subx", "subx",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_addx, { 0x10 },
+    & ifmt_add, { 0x10 },
     (PTR) & fmt_addx_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -2554,7 +2448,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_TRAP, "trap", "trap",
     { { MNEM, ' ', OP (UIMM4), 0 } },
-    & fmt_trap, { 0x10f0 },
+    & ifmt_trap, { 0x10f0 },
     (PTR) & fmt_trap_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2563,7 +2457,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_UNLOCK, "unlock", "unlock",
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
-    & fmt_unlock, { 0x2050 },
+    & ifmt_cmp, { 0x2050 },
     (PTR) & fmt_unlock_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2573,7 +2467,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SATB, "satb", "satb",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_satb, { 0x80600300 },
+    & ifmt_satb, { 0x80600300 },
     (PTR) & fmt_satb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2584,7 +2478,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SATH, "sath", "sath",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_satb, { 0x80600200 },
+    & ifmt_satb, { 0x80600200 },
     (PTR) & fmt_satb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2595,7 +2489,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SAT, "sat", "sat",
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
-    & fmt_sat, { 0x80600000 },
+    & ifmt_satb, { 0x80600000 },
     (PTR) & fmt_sat_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2606,7 +2500,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
     { { MNEM, ' ', OP (SRC2), 0 } },
-    & fmt_cmpz, { 0x370 },
+    & ifmt_cmpz, { 0x370 },
     (PTR) & fmt_cmpz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
@@ -2617,7 +2511,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SADD, "sadd", "sadd",
     { { MNEM, 0 } },
-    & fmt_sadd, { 0x50e4 },
+    & ifmt_sadd, { 0x50e4 },
     (PTR) & fmt_sadd_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2628,7 +2522,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACWU1, "macwu1", "macwu1",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_macwu1, { 0x50b0 },
+    & ifmt_cmpeq, { 0x50b0 },
     (PTR) & fmt_macwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2639,8 +2533,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MSBLO, "msblo", "msblo",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_machi, { 0x50d0 },
-    (PTR) & fmt_machi_ops[0],
+    & ifmt_cmpeq, { 0x50d0 },
+    (PTR) & fmt_msblo_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
@@ -2650,7 +2544,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_mulwu1, { 0x50a0 },
+    & ifmt_cmpeq, { 0x50a0 },
     (PTR) & fmt_mulwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2661,7 +2555,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_MACLH1, "maclh1", "maclh1",
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
-    & fmt_macwu1, { 0x50c0 },
+    & ifmt_cmpeq, { 0x50c0 },
     (PTR) & fmt_macwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -2672,7 +2566,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SC, "sc", "sc",
     { { MNEM, 0 } },
-    & fmt_sc, { 0x7401 },
+    & ifmt_sadd, { 0x7401 },
     (PTR) & fmt_sc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2683,7 +2577,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     M32R_INSN_SNC, "snc", "snc",
     { { MNEM, 0 } },
-    & fmt_sc, { 0x7501 },
+    & ifmt_sadd, { 0x7501 },
     (PTR) & fmt_sc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2706,163 +2600,163 @@ static const CGEN_INSN_TABLE insn_table =
 
 #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
 
-static const CGEN_IFMT fmt_bc8r = {
+static const CGEN_IFMT ifmt_bc8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
-static const CGEN_IFMT fmt_bc24r = {
+static const CGEN_IFMT ifmt_bc24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
-static const CGEN_IFMT fmt_bl8r = {
+static const CGEN_IFMT ifmt_bl8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
-static const CGEN_IFMT fmt_bl24r = {
+static const CGEN_IFMT ifmt_bl24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_bcl8r = {
+static const CGEN_IFMT ifmt_bcl8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_bcl24r = {
+static const CGEN_IFMT ifmt_bcl24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_bnc8r = {
+static const CGEN_IFMT ifmt_bnc8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
-static const CGEN_IFMT fmt_bnc24r = {
+static const CGEN_IFMT ifmt_bnc24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
-static const CGEN_IFMT fmt_bra8r = {
+static const CGEN_IFMT ifmt_bra8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
-static const CGEN_IFMT fmt_bra24r = {
+static const CGEN_IFMT ifmt_bra24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_bncl8r = {
+static const CGEN_IFMT ifmt_bncl8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_bncl24r = {
+static const CGEN_IFMT ifmt_bncl24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_ld_2 = {
+static const CGEN_IFMT ifmt_ld_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_ld_d2 = {
+static const CGEN_IFMT ifmt_ld_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_ldb_2 = {
+static const CGEN_IFMT ifmt_ldb_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_ldb_d2 = {
+static const CGEN_IFMT ifmt_ldb_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_ldh_2 = {
+static const CGEN_IFMT ifmt_ldh_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_ldh_d2 = {
+static const CGEN_IFMT ifmt_ldh_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_ldub_2 = {
+static const CGEN_IFMT ifmt_ldub_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_ldub_d2 = {
+static const CGEN_IFMT ifmt_ldub_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_lduh_2 = {
+static const CGEN_IFMT ifmt_lduh_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_lduh_d2 = {
+static const CGEN_IFMT ifmt_lduh_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_pop = {
+static const CGEN_IFMT ifmt_pop = {
   16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_ldi8a = {
+static const CGEN_IFMT ifmt_ldi8a = {
   16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
 };
 
-static const CGEN_IFMT fmt_ldi16a = {
+static const CGEN_IFMT ifmt_ldi16a = {
   32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_rac_d = {
+static const CGEN_IFMT ifmt_rac_d = {
   16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_rac_ds = {
+static const CGEN_IFMT ifmt_rac_ds = {
   16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_rach_d = {
+static const CGEN_IFMT ifmt_rach_d = {
   16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
 };
 
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
-static const CGEN_IFMT fmt_rach_ds = {
+static const CGEN_IFMT ifmt_rach_ds = {
   16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
 };
 
 /* end-sanitize-m32rx */
-static const CGEN_IFMT fmt_st_2 = {
+static const CGEN_IFMT ifmt_st_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_st_d2 = {
+static const CGEN_IFMT ifmt_st_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_stb_2 = {
+static const CGEN_IFMT ifmt_stb_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_stb_d2 = {
+static const CGEN_IFMT ifmt_stb_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_sth_2 = {
+static const CGEN_IFMT ifmt_sth_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
-static const CGEN_IFMT fmt_sth_d2 = {
+static const CGEN_IFMT ifmt_sth_d2 = {
   32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT fmt_push = {
+static const CGEN_IFMT ifmt_push = {
   16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
@@ -2883,7 +2777,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bc8r", "bc",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bc8r, { 0x7c00 },
+    & ifmt_bc8r, { 0x7c00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2892,7 +2786,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bc24r", "bc",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bc24r, { 0xfc000000 },
+    & ifmt_bc24r, { 0xfc000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2901,7 +2795,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bl8r", "bl",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bl8r, { 0x7e00 },
+    & ifmt_bl8r, { 0x7e00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2910,7 +2804,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bl24r", "bl",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bl24r, { 0xfe000000 },
+    & ifmt_bl24r, { 0xfe000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2920,7 +2814,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bcl8r", "bcl",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bcl8r, { 0x7800 },
+    & ifmt_bcl8r, { 0x7800 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2931,7 +2825,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bcl24r", "bcl",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bcl24r, { 0xf8000000 },
+    & ifmt_bcl24r, { 0xf8000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2941,7 +2835,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bnc8r", "bnc",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bnc8r, { 0x7d00 },
+    & ifmt_bnc8r, { 0x7d00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2950,7 +2844,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bnc24r", "bnc",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bnc24r, { 0xfd000000 },
+    & ifmt_bnc24r, { 0xfd000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2959,7 +2853,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bra8r", "bra",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bra8r, { 0x7f00 },
+    & ifmt_bra8r, { 0x7f00 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -2968,7 +2862,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bra24r", "bra",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bra24r, { 0xff000000 },
+    & ifmt_bra24r, { 0xff000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -2978,7 +2872,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bncl8r", "bncl",
     { { MNEM, ' ', OP (DISP8), 0 } },
-    & fmt_bncl8r, { 0x7900 },
+    & ifmt_bncl8r, { 0x7900 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
   },
@@ -2989,7 +2883,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "bncl24r", "bncl",
     { { MNEM, ' ', OP (DISP24), 0 } },
-    & fmt_bncl24r, { 0xf9000000 },
+    & ifmt_bncl24r, { 0xf9000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
@@ -2999,7 +2893,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ld-2", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
-    & fmt_ld_2, { 0x20c0 },
+    & ifmt_ld_2, { 0x20c0 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3008,7 +2902,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ld-d2", "ld",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
-    & fmt_ld_d2, { 0xa0c00000 },
+    & ifmt_ld_d2, { 0xa0c00000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3017,7 +2911,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldb-2", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
-    & fmt_ldb_2, { 0x2080 },
+    & ifmt_ldb_2, { 0x2080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3026,7 +2920,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldb-d2", "ldb",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
-    & fmt_ldb_d2, { 0xa0800000 },
+    & ifmt_ldb_d2, { 0xa0800000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3035,7 +2929,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldh-2", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
-    & fmt_ldh_2, { 0x20a0 },
+    & ifmt_ldh_2, { 0x20a0 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3044,7 +2938,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldh-d2", "ldh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
-    & fmt_ldh_d2, { 0xa0a00000 },
+    & ifmt_ldh_d2, { 0xa0a00000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3053,7 +2947,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldub-2", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
-    & fmt_ldub_2, { 0x2090 },
+    & ifmt_ldub_2, { 0x2090 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3062,7 +2956,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldub-d2", "ldub",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
-    & fmt_ldub_d2, { 0xa0900000 },
+    & ifmt_ldub_d2, { 0xa0900000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3071,7 +2965,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "lduh-2", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
-    & fmt_lduh_2, { 0x20b0 },
+    & ifmt_lduh_2, { 0x20b0 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3080,7 +2974,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "lduh-d2", "lduh",
     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
-    & fmt_lduh_d2, { 0xa0b00000 },
+    & ifmt_lduh_d2, { 0xa0b00000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3089,7 +2983,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "pop", "pop",
     { { MNEM, ' ', OP (DR), 0 } },
-    & fmt_pop, { 0x20ef },
+    & ifmt_pop, { 0x20ef },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3098,7 +2992,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldi8a", "ldi",
     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
-    & fmt_ldi8a, { 0x6000 },
+    & ifmt_ldi8a, { 0x6000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
   },
@@ -3107,7 +3001,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "ldi16a", "ldi",
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
-    & fmt_ldi16a, { 0x90f00000 },
+    & ifmt_ldi16a, { 0x90f00000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3117,7 +3011,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "rac-d", "rac",
     { { MNEM, ' ', OP (ACCD), 0 } },
-    & fmt_rac_d, { 0x5090 },
+    & ifmt_rac_d, { 0x5090 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -3128,7 +3022,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "rac-ds", "rac",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
-    & fmt_rac_ds, { 0x5090 },
+    & ifmt_rac_ds, { 0x5090 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -3139,7 +3033,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "rach-d", "rach",
     { { MNEM, ' ', OP (ACCD), 0 } },
-    & fmt_rach_d, { 0x5080 },
+    & ifmt_rach_d, { 0x5080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -3150,7 +3044,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "rach-ds", "rach",
     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
-    & fmt_rach_ds, { 0x5080 },
+    & ifmt_rach_ds, { 0x5080 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
@@ -3160,7 +3054,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "st-2", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
-    & fmt_st_2, { 0x2040 },
+    & ifmt_st_2, { 0x2040 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3169,7 +3063,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "st-d2", "st",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
-    & fmt_st_d2, { 0xa0400000 },
+    & ifmt_st_d2, { 0xa0400000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3178,7 +3072,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "stb-2", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
-    & fmt_stb_2, { 0x2000 },
+    & ifmt_stb_2, { 0x2000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3187,7 +3081,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "stb-d2", "stb",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
-    & fmt_stb_d2, { 0xa0000000 },
+    & ifmt_stb_d2, { 0xa0000000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3196,7 +3090,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "sth-2", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
-    & fmt_sth_2, { 0x2020 },
+    & ifmt_sth_2, { 0x2020 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
@@ -3205,7 +3099,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "sth-d2", "sth",
     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
-    & fmt_sth_d2, { 0xa0200000 },
+    & ifmt_sth_d2, { 0xa0200000 },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
@@ -3214,7 +3108,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
     { 1, 1, 1, 1 },
     -1, "push", "push",
     { { MNEM, ' ', OP (SRC1), 0 } },
-    & fmt_push, { 0x207f },
+    & ifmt_push, { 0x207f },
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
-- 
2.7.4