From 8049edb65383419a802d20e251d9530981d91d7e Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 30 Jun 2022 17:28:46 +0800 Subject: [PATCH] radeonsi: implement nir_intrinsic_load_num_vertices_per_primitive_amd Acked-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 1 + src/gallium/drivers/radeonsi/si_shader_llvm.c | 34 +++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index fdcb3c5..3d1a30b 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3605,6 +3605,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_tcs_num_patches_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd: case nir_intrinsic_load_clip_half_line_width_amd: + case nir_intrinsic_load_num_vertices_per_primitive_amd: case nir_intrinsic_load_cull_ccw_amd: case nir_intrinsic_load_cull_any_enabled_amd: case nir_intrinsic_load_cull_back_face_enabled_amd: diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index f0854d9..38ef0df 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -30,6 +30,7 @@ #include "sid.h" #include "tgsi/tgsi_from_mesa.h" #include "util/u_memory.h" +#include "util/u_prim.h" struct si_llvm_diagnostics { struct util_debug_callback *debug; @@ -717,6 +718,36 @@ void si_build_wrapper_function(struct si_shader_context *ctx, LLVMValueRef *part LLVMBuildRet(builder, ret); } +static LLVMValueRef si_get_num_vertices_per_prim(struct si_shader_context *ctx) +{ + const struct si_shader_info *info = &ctx->shader->selector->info; + + unsigned num_vertices; + if (ctx->stage == MESA_SHADER_GEOMETRY) { + num_vertices = u_vertices_per_prim(info->base.gs.output_primitive); + } else if (ctx->stage == MESA_SHADER_VERTEX) { + if (info->base.vs.blit_sgprs_amd) { + num_vertices = 3; + } else if (ctx->shader->key.ge.opt.ngg_culling & SI_NGG_CULL_LINES) { + num_vertices = 2; + } else { + /* Extract OUTPRIM field. */ + LLVMValueRef num = GET_FIELD(ctx, GS_STATE_OUTPRIM); + return LLVMBuildAdd(ctx->ac.builder, num, ctx->ac.i32_1, ""); + } + } else { + assert(ctx->stage == MESA_SHADER_TESS_EVAL); + + if (info->base.tess.point_mode) + num_vertices = 1; + else if (info->base.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES) + num_vertices = 2; + else + num_vertices = 3; + } + return LLVMConstInt(ctx->ac.i32, num_vertices, false); +} + static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op) { struct si_shader_context *ctx = si_shader_context_from_abi(abi); @@ -813,6 +844,9 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin return LLVMBuildBitCast(ctx->ac.builder, terms, ctx->ac.v4f32, ""); } + case nir_intrinsic_load_num_vertices_per_primitive_amd: + return si_get_num_vertices_per_prim(ctx); + case nir_intrinsic_load_cull_ccw_amd: /* radeonsi embed cw/ccw info into front/back face enabled */ return ctx->ac.i1false; -- 2.7.4