From 801b2b05c39048c8d770a387b9d272d7e7e132e1 Mon Sep 17 00:00:00 2001 From: "palfia@homejinni.com" Date: Mon, 2 Dec 2013 21:17:16 +0000 Subject: [PATCH] MIPS: Refactor BinaryOpIC to be able to use different stubs. Port r18191 (c20c6dc1) Original commit message: Previously BinaryOpIC and BinaryOpStub were pretty much interdependent. However, in order to use allocation sites for string adds on-demand, we need to be able to use different stubs (with a different number of register parameters, via trampolines) depending on the BinaryOpIC state. BUG= R=plind44@gmail.com Review URL: https://codereview.chromium.org/100023002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18213 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/mips/code-stubs-mips.cc | 4 ++-- src/mips/full-codegen-mips.cc | 7 +++---- src/mips/lithium-codegen-mips.cc | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/mips/code-stubs-mips.cc b/src/mips/code-stubs-mips.cc index 4b71e3f..4c3708c 100644 --- a/src/mips/code-stubs-mips.cc +++ b/src/mips/code-stubs-mips.cc @@ -1261,7 +1261,7 @@ void StoreBufferOverflowStub::Generate(MacroAssembler* masm) { } -void BinaryOpStub::InitializeInterfaceDescriptor( +void BinaryOpICStub::InitializeInterfaceDescriptor( Isolate* isolate, CodeStubInterfaceDescriptor* descriptor) { static Register registers[] = { a1, a0 }; @@ -1735,7 +1735,7 @@ void CodeStub::GenerateStubsAheadOfTime(Isolate* isolate) { StubFailureTrampolineStub::GenerateAheadOfTime(isolate); ArrayConstructorStubBase::GenerateStubsAheadOfTime(isolate); CreateAllocationSiteStub::GenerateAheadOfTime(isolate); - BinaryOpStub::GenerateAheadOfTime(isolate); + BinaryOpICStub::GenerateAheadOfTime(isolate); } diff --git a/src/mips/full-codegen-mips.cc b/src/mips/full-codegen-mips.cc index a56fbb1..3ce2ab5 100644 --- a/src/mips/full-codegen-mips.cc +++ b/src/mips/full-codegen-mips.cc @@ -2319,7 +2319,7 @@ void FullCodeGenerator::EmitInlineSmiBinaryOp(BinaryOperation* expr, patch_site.EmitJumpIfSmi(scratch1, &smi_case); __ bind(&stub_call); - BinaryOpStub stub(op, mode); + BinaryOpICStub stub(op, mode); CallIC(stub.GetCode(isolate()), RelocInfo::CODE_TARGET, expr->BinaryOperationFeedbackId()); patch_site.EmitPatchInfo(); @@ -2328,7 +2328,6 @@ void FullCodeGenerator::EmitInlineSmiBinaryOp(BinaryOperation* expr, __ bind(&smi_case); // Smi case. This code works the same way as the smi-smi case in the type // recording binary operation stub, see - // BinaryOpStub::GenerateSmiSmiOperation for comments. switch (op) { case Token::SAR: __ Branch(&stub_call); @@ -2402,7 +2401,7 @@ void FullCodeGenerator::EmitBinaryOp(BinaryOperation* expr, OverwriteMode mode) { __ mov(a0, result_register()); __ pop(a1); - BinaryOpStub stub(op, mode); + BinaryOpICStub stub(op, mode); JumpPatchSite patch_site(masm_); // unbound, signals no inlined smi code. CallIC(stub.GetCode(isolate()), RelocInfo::CODE_TARGET, expr->BinaryOperationFeedbackId()); @@ -4474,7 +4473,7 @@ void FullCodeGenerator::VisitCountOperation(CountOperation* expr) { // Record position before stub call. SetSourcePosition(expr->position()); - BinaryOpStub stub(Token::ADD, NO_OVERWRITE); + BinaryOpICStub stub(Token::ADD, NO_OVERWRITE); CallIC(stub.GetCode(isolate()), RelocInfo::CODE_TARGET, expr->CountBinOpFeedbackId()); diff --git a/src/mips/lithium-codegen-mips.cc b/src/mips/lithium-codegen-mips.cc index 8809869..566d0bc 100644 --- a/src/mips/lithium-codegen-mips.cc +++ b/src/mips/lithium-codegen-mips.cc @@ -2000,7 +2000,7 @@ void LCodeGen::DoArithmeticT(LArithmeticT* instr) { ASSERT(ToRegister(instr->right()).is(a0)); ASSERT(ToRegister(instr->result()).is(v0)); - BinaryOpStub stub(instr->op(), NO_OVERWRITE); + BinaryOpICStub stub(instr->op(), NO_OVERWRITE); CallCode(stub.GetCode(isolate()), RelocInfo::CODE_TARGET, instr); // Other arch use a nop here, to signal that there is no inlined // patchable code. Mips does not need the nop, since our marker -- 2.7.4