From 800e1005881fb6786960289fbc5f88ee17637f48 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Tue, 9 Jun 2020 10:43:59 +0000 Subject: [PATCH] Revert "[Alignment][NFC] Migrate TargetLowering::allowsMemoryAccess" This reverts commit f21c52667ed147903015a94643b0057319189d4e. --- llvm/include/llvm/CodeGen/TargetLowering.h | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++-- llvm/lib/CodeGen/TargetLoweringBase.cpp | 16 +++++++--------- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 8 ++++---- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 5 ++--- 5 files changed, 16 insertions(+), 19 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 934cdd5..199ed0b 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -1609,7 +1609,7 @@ public: /// target). virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, - unsigned AddrSpace = 0, Align Alignment = Align(1), + unsigned AddrSpace = 0, unsigned Alignment = 1, MachineMemOperand::Flags Flags = MachineMemOperand::MONone, bool *Fast = nullptr) const; diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ee2c621..e3275cae 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4862,7 +4862,7 @@ bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST, // Ensure that this isn't going to produce an unsupported memory access. if (ShAmt && !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, - LDST->getAddressSpace(), Align(ShAmt / 8), + LDST->getAddressSpace(), ShAmt / 8, LDST->getMemOperand()->getFlags())) return false; @@ -8478,7 +8478,7 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) { SDLoc DL(RHS); uint64_t PtrOff = IsFSHL ? (((BitWidth - ShAmt) % BitWidth) / 8) : (ShAmt / 8); - const Align NewAlign = commonAlignment(RHS->getAlign(), PtrOff); + unsigned NewAlign = MinAlign(RHS->getAlignment(), PtrOff); bool Fast = false; if (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, RHS->getAddressSpace(), NewAlign, diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 538e1fe..6ec6498 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1599,21 +1599,19 @@ bool TargetLoweringBase::allowsMemoryAccessForAlignment( Fast); } -bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, - const DataLayout &DL, EVT VT, - unsigned AddrSpace, Align Alignment, - MachineMemOperand::Flags Flags, - bool *Fast) const { - return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, - Alignment.value(), Flags, Fast); +bool TargetLoweringBase::allowsMemoryAccess( + LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, + unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { + return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, + Flags, Fast); } bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast) const { - return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), - MMO.getFlags(), Fast); + return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), + MMO.getAlign().value(), MMO.getFlags(), Fast); } BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 9fee321..99d70a0 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3385,12 +3385,12 @@ EVT HexagonTargetLowering::getOptimalMemOpType( return MVT::Other; } -bool HexagonTargetLowering::allowsMemoryAccess( - LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, - Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { +bool HexagonTargetLowering::allowsMemoryAccess(LLVMContext &Context, + const DataLayout &DL, EVT VT, unsigned AddrSpace, unsigned Alignment, + MachineMemOperand::Flags Flags, bool *Fast) const { MVT SVT = VT.getSimpleVT(); if (Subtarget.isHVXVectorType(SVT, true)) - return allowsHvxMemoryAccess(SVT, Alignment.value(), Flags, Fast); + return allowsHvxMemoryAccess(SVT, Alignment, Flags, Fast); return TargetLoweringBase::allowsMemoryAccess( Context, DL, VT, AddrSpace, Alignment, Flags, Fast); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 511363a..1c123c0 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -306,9 +306,8 @@ namespace HexagonISD { const AttributeList &FuncAttributes) const override; bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, - unsigned AddrSpace, Align Alignment, - MachineMemOperand::Flags Flags, - bool *Fast) const override; + unsigned AddrSpace, unsigned Alignment, MachineMemOperand::Flags Flags, + bool *Fast) const override; bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) -- 2.7.4