From 7fa8af30ecdf94d531f97ea9df42927ab4ebb70a Mon Sep 17 00:00:00 2001 From: Luiz Angelo Daros de Luca Date: Fri, 28 Jan 2022 03:05:05 -0300 Subject: [PATCH] net: dsa: realtek: rtl8365mb: use DSA CPU port MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Instead of a fixed CPU port, assume that DSA is correct. Signed-off-by: Luiz Angelo Daros de Luca Tested-by: Arınç ÜNAL Reviewed-by: Alvin Šipraga Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/dsa/realtek/rtl8365mb.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index c2e6ec2..d580afc 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -103,7 +103,6 @@ /* Chip-specific data and limits */ #define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 -#define RTL8365MB_CPU_PORT_NUM_8365MB_VC 6 #define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC 2112 static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1 }; @@ -111,7 +110,7 @@ static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1 }; #define RTL8365MB_PHYADDRMAX 7 #define RTL8365MB_NUM_PHYREGS 32 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) -#define RTL8365MB_MAX_NUM_PORTS (RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1) +#define RTL8365MB_MAX_NUM_PORTS 7 /* Chip identification registers */ #define RTL8365MB_CHIP_ID_REG 0x1300 @@ -1821,6 +1820,7 @@ static int rtl8365mb_reset_chip(struct realtek_priv *priv) static int rtl8365mb_setup(struct dsa_switch *ds) { struct realtek_priv *priv = ds->priv; + struct dsa_port *cpu_dp; struct rtl8365mb *mb; int ret; int i; @@ -1848,9 +1848,17 @@ static int rtl8365mb_setup(struct dsa_switch *ds) dev_info(priv->dev, "no interrupt support\n"); /* Configure CPU tagging */ - ret = rtl8365mb_cpu_config(priv); - if (ret) - goto out_teardown_irq; + /* Currently, only one CPU port is supported */ + dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) { + priv->cpu_port = cpu_dp->index; + mb->cpu.mask = BIT(priv->cpu_port); + mb->cpu.trap_port = priv->cpu_port; + ret = rtl8365mb_cpu_config(priv); + if (ret) + goto out_teardown_irq; + + break; + } /* Configure ports */ for (i = 0; i < priv->num_ports; i++) { @@ -1962,8 +1970,7 @@ static int rtl8365mb_detect(struct realtek_priv *priv) "found an RTL8365MB-VC switch (ver=0x%04x)\n", chip_ver); - priv->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC; - priv->num_ports = priv->cpu_port + 1; + priv->num_ports = RTL8365MB_MAX_NUM_PORTS; mb->priv = priv; mb->chip_id = chip_id; @@ -1974,8 +1981,6 @@ static int rtl8365mb_detect(struct realtek_priv *priv) mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); mb->cpu.enable = 1; - mb->cpu.mask = BIT(priv->cpu_port); - mb->cpu.trap_port = priv->cpu_port; mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; -- 2.7.4