From 7f83f71031f2f750dac396c120fc5cd5941be4ae Mon Sep 17 00:00:00 2001 From: sivarv Date: Fri, 11 Nov 2016 16:41:16 -0800 Subject: [PATCH] Generate inc/dec [mem] instead of add/sub [mem], 1 for read-modify-write operations. Commit migrated from https://github.com/dotnet/coreclr/commit/8753709778f4282b16647946dfe61cfd8f8414e5 --- src/coreclr/src/jit/codegenxarch.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/coreclr/src/jit/codegenxarch.cpp b/src/coreclr/src/jit/codegenxarch.cpp index 36a6cf5..5e4153c 100644 --- a/src/coreclr/src/jit/codegenxarch.cpp +++ b/src/coreclr/src/jit/codegenxarch.cpp @@ -4533,6 +4533,22 @@ void CodeGen::genStoreInd(GenTreePtr node) assert(rmwSrc == data->gtGetOp2()); genCodeForShiftRMW(storeInd); } + else if (data->OperGet() == GT_ADD && rmwSrc->IsIntegralConst(1)) + { + // Generate inc [mem] instead of "add [mem], 1". + // Note that we don't need to check for GT_SUB of -1 because + // global morph would transform it to GT_ADD of 1. + assert(rmwSrc->isContainedIntOrIImmed()); + getEmitter()->emitInsRMW(INS_inc, emitTypeSize(storeInd), storeInd); + } + else if (data->OperGet() == GT_ADD && rmwSrc->IsIntegralConst(-1)) + { + // Generate dec [mem] instead of "add [mem], -1". + // Note that we don't need to check for GT_SUB of 1 because + // global morph would transform it to GT_ADD of -1. + assert(rmwSrc->isContainedIntOrIImmed()); + getEmitter()->emitInsRMW(INS_dec, emitTypeSize(storeInd), storeInd); + } else { // generate code for remaining binary RMW memory ops like add/sub/and/or/xor -- 2.7.4