From 7ef869ef6876a511c68da0592209442d16d36f0c Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Thu, 11 Jun 2020 14:09:16 +0800 Subject: [PATCH] drm/amdgpu/sriov: Need to clear kiq position As will clear vf fw during unload driver, to avoid idle fail. Need to clear KIQ portion also. Signed-off-by: Emily Deng Ack-by: Monk.liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e9045dde5b24..323285eb1457 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6876,6 +6876,7 @@ static int gfx_v10_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; + uint32_t tmp; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -6890,6 +6891,11 @@ static int gfx_v10_0_hw_fini(void *handle) DRM_ERROR("KCQ disable failed\n"); if (amdgpu_sriov_vf(adev)) { gfx_v10_0_cp_gfx_enable(adev, false); + /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ + tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); + tmp &= 0xffffff00; + WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); + return 0; } gfx_v10_0_cp_enable(adev, false); -- 2.34.1