From 7e9a6620d5c3a9ac048d2cb5d1d116385ef31877 Mon Sep 17 00:00:00 2001 From: Amit Cohen Date: Sun, 29 Nov 2020 14:53:59 +0200 Subject: [PATCH] mlxsw: reg: Add Switch Port VLAN Classification Register SPVC configures the port to identify packets as untagged / single tagged / double tagged packets based on the packet EtherTypes. It will be used to classify 802.1q packets as untagged and 802.1ad packets as tagged when received by ports member in a 802.1ad bridge. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 99 +++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index fcf9095..5248532 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -1857,6 +1857,104 @@ static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, } } +/* SPVC - Switch Port VLAN Classification Register + * ----------------------------------------------- + * Configures the port to identify packets as untagged / single tagged / + * double packets based on the packet EtherTypes. + * Ethertype IDs are configured by SVER. + */ +#define MLXSW_REG_SPVC_ID 0x2026 +#define MLXSW_REG_SPVC_LEN 0x0C + +MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); + +/* reg_spvc_local_port + * Local port. + * Access: Index + * + * Note: applies both to Rx port and Tx port, so if a packet traverses + * through Rx port i and a Tx port j then port i and port j must have the + * same configuration. + */ +MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8); + +/* reg_spvc_inner_et2 + * Vlan Tag1 EtherType2 enable. + * Packet is initially classified as double VLAN Tag if in addition to + * being classified with a tag0 VLAN Tag its tag1 EtherType value is + * equal to ether_type2. + * 0: disable (default) + * 1: enable + * Access: RW + */ +MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); + +/* reg_spvc_et2 + * Vlan Tag0 EtherType2 enable. + * Packet is initially classified as VLAN Tag if its tag0 EtherType is + * equal to ether_type2. + * 0: disable (default) + * 1: enable + * Access: RW + */ +MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); + +/* reg_spvc_inner_et1 + * Vlan Tag1 EtherType1 enable. + * Packet is initially classified as double VLAN Tag if in addition to + * being classified with a tag0 VLAN Tag its tag1 EtherType value is + * equal to ether_type1. + * 0: disable + * 1: enable (default) + * Access: RW + */ +MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); + +/* reg_spvc_et1 + * Vlan Tag0 EtherType1 enable. + * Packet is initially classified as VLAN Tag if its tag0 EtherType is + * equal to ether_type1. + * 0: disable + * 1: enable (default) + * Access: RW + */ +MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); + +/* reg_inner_et0 + * Vlan Tag1 EtherType0 enable. + * Packet is initially classified as double VLAN Tag if in addition to + * being classified with a tag0 VLAN Tag its tag1 EtherType value is + * equal to ether_type0. + * 0: disable + * 1: enable (default) + * Access: RW + */ +MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); + +/* reg_et0 + * Vlan Tag0 EtherType0 enable. + * Packet is initially classified as VLAN Tag if its tag0 EtherType is + * equal to ether_type0. + * 0: disable + * 1: enable (default) + * Access: RW + */ +MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); + +static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1, + bool et0) +{ + MLXSW_REG_ZERO(spvc, payload); + mlxsw_reg_spvc_local_port_set(payload, local_port); + /* Enable inner_et1 and inner_et0 to enable identification of double + * tagged packets. + */ + mlxsw_reg_spvc_inner_et1_set(payload, 1); + mlxsw_reg_spvc_inner_et0_set(payload, 1); + mlxsw_reg_spvc_et1_set(payload, et1); + mlxsw_reg_spvc_et0_set(payload, et0); +} + /* CWTP - Congetion WRED ECN TClass Profile * ---------------------------------------- * Configures the profiles for queues of egress port and traffic class @@ -11212,6 +11310,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(svpe), MLXSW_REG(sfmr), MLXSW_REG(spvmlr), + MLXSW_REG(spvc), MLXSW_REG(cwtp), MLXSW_REG(cwtpm), MLXSW_REG(pgcr), -- 2.7.4