From 7e287609e338a1744ddaedf8b2d75acff4e02e6d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 15 Nov 2022 07:16:28 +0000 Subject: [PATCH] radv: use HTILE for VRS image only on GFX10.3 Based on registers, GFX11 no longer uses HTILE. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 5 +++-- src/amd/vulkan/radv_image.c | 6 ++++-- src/amd/vulkan/radv_private.h | 6 ++++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1a89790..3edc5d4 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3338,7 +3338,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) */ radv_load_ds_clear_metadata(cmd_buffer, iview); } - } else if (render->vrs_att.iview && radv_cmd_buffer_get_vrs_image(cmd_buffer)) { + } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10_3 && + render->vrs_att.iview && radv_cmd_buffer_get_vrs_image(cmd_buffer)) { /* When a subpass uses a VRS attachment without binding a depth/stencil attachment, we have to * bind our internal depth buffer that contains the VRS data as part of HTILE. */ @@ -7062,7 +7063,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe render->vrs_texel_size = vrs_texel_size; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER; - if (render->vrs_att.iview) { + if (render->vrs_att.iview && cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10_3) { if (render->ds_att.iview) { /* When we have a VRS attachment and a depth/stencil attachment, we just need to copy the * VRS rates to the HTILE buffer of the attachment. diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index a7285ca..c4d10ae 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -344,6 +344,8 @@ radv_use_fmask_for_image(const struct radv_device *device, const struct radv_ima static inline bool radv_use_htile_for_image(const struct radv_device *device, const struct radv_image *image) { + const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; + /* TODO: * - Investigate about mips+layers. * - Enable on other gens. @@ -357,11 +359,11 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima return false; /* Do not enable HTILE for very small images because it seems less performant but make sure it's - * allowed with VRS attachments because we need HTILE. + * allowed with VRS attachments because we need HTILE on GFX10.3. */ if (image->info.width * image->info.height < 8 * 8 && !(device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS) && - !device->attachment_vrs_enabled) + !(gfx_level == GFX10_3 && device->attachment_vrs_enabled)) return false; return (image->info.levels == 1 || use_htile_for_mips) && !image->shareable; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index a68ff49..56e83d0 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2440,8 +2440,10 @@ radv_image_has_htile(const struct radv_image *image) static inline bool radv_image_has_vrs_htile(const struct radv_device *device, const struct radv_image *image) { - /* Any depth buffer can potentially use VRS. */ - return device->attachment_vrs_enabled && radv_image_has_htile(image) && + const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; + + /* Any depth buffer can potentially use VRS on GFX10.3. */ + return gfx_level == GFX10_3 && device->attachment_vrs_enabled && radv_image_has_htile(image) && (image->vk.usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT); } -- 2.7.4