From 7e21910f233a8ff6e2c4adaee6b4edd2f70b6c68 Mon Sep 17 00:00:00 2001 From: Chad Versace Date: Wed, 9 Jan 2013 11:35:47 -0800 Subject: [PATCH] i965: Add opcodes for F32TO16 and F16TO32 The GLSL ES 3.00 operations packHalf2x16 and unpackHalf2x16 will emit these opcodes. - Define the opcodes BRW_OPCODE_{F32TO16,F16TO32}. - Add the opcodes to the brw_disasm table. - Define convenience functions brw_{F32TO16,F16TO32}. Reviewed-by: Ian Romanick Acked-by: Paul Berry Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_defines.h | 2 ++ src/mesa/drivers/dri/i965/brw_disasm.c | 2 ++ src/mesa/drivers/dri/i965/brw_eu.h | 2 ++ src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 8c8895e..e2f1e65 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -644,6 +644,8 @@ enum opcode { BRW_OPCODE_ASR = 12, BRW_OPCODE_CMP = 16, BRW_OPCODE_CMPN = 17, + BRW_OPCODE_F32TO16 = 19, + BRW_OPCODE_F16TO32 = 20, BRW_OPCODE_JMPI = 32, BRW_OPCODE_IF = 34, BRW_OPCODE_IFF = 35, diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 1621769..50551f4 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -41,6 +41,8 @@ const struct opcode_desc opcode_descs[128] = { [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 }, [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 }, [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 }, [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 7b874c7..06daaba 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -157,6 +157,8 @@ ALU2(SHL) ALU2(RSR) ALU2(RSL) ALU2(ASR) +ALU1(F32TO16) +ALU1(F16TO32) ALU2(JMPI) ALU2(ADD) ALU2(AVG) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index bd9c182..fecbff1 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -907,6 +907,8 @@ ALU2(SHL) ALU2(RSR) ALU2(RSL) ALU2(ASR) +ALU1(F32TO16) +ALU1(F16TO32) ALU1(FRC) ALU1(RNDD) ALU2(MAC) -- 2.7.4