From 7e123255861a3d74306ed1b0ceebd9d1725c84f0 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 24 Jan 2020 10:12:34 +0000
Subject: [PATCH] [X86] Add test showing failure to remove vector rotate of
 allsignbits

Rotating an 0/-1 value by any amount will always result in the same 0/-1 value
---
 llvm/test/CodeGen/X86/rotate_vec.ll | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/CodeGen/X86/rotate_vec.ll b/llvm/test/CodeGen/X86/rotate_vec.ll
index 36594aa..cf1a90a 100644
--- a/llvm/test/CodeGen/X86/rotate_vec.ll
+++ b/llvm/test/CodeGen/X86/rotate_vec.ll
@@ -85,4 +85,22 @@ define <4 x i32> @rot_v4i32_zero_non_splat(<4 x i32> %x) {
   %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %2
 }
+
+define <4 x i32> @rot_v4i32_allsignbits(<4 x i32> %x, <4 x i32> %y) {
+; XOP-LABEL: rot_v4i32_allsignbits:
+; XOP:       # %bb.0:
+; XOP-NEXT:    vpsrad $31, %xmm0, %xmm0
+; XOP-NEXT:    vprotd %xmm1, %xmm0, %xmm0
+; XOP-NEXT:    retq
+;
+; AVX512-LABEL: rot_v4i32_allsignbits:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vpsrad $31, %xmm0, %xmm0
+; AVX512-NEXT:    vprolvd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    retq
+  %1 = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> %y)
+  ret <4 x i32> %2
+}
+
 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
-- 
2.7.4