From 7d93d538710708a27ca1a6ae8f28ddbf47d876fa Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Thu, 16 Apr 1998 07:49:58 +0000 Subject: [PATCH] o CVT.S.W and CVT.W.S were reversed o When unpacking an r5900 FP value, was not treating IEEE-NaN's as very large values. o When packing an r5900 FP result from an infinite precision intermediate value was saturating to IEEE-MAX instead of r5900-MAX o The least significant bit of the FP status register did not stick to one. --- sim/common/ChangeLog | 7 +++++++ sim/common/sim-fpu.c | 43 ++++++++++++++++++++++++++++++++++++++++--- sim/mips/ChangeLog | 18 ++++++++++++++++++ 3 files changed, 65 insertions(+), 3 deletions(-) diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index 3b2e9ed..fa67c10 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,10 @@ +Thu Apr 16 10:30:14 1998 Andrew Cagney + + * sim-fpu.c, sim-fpu.h (sim_fpu_fractionto, sim_fpu_tofraction): + New functions, pack / unpack sim_fpu struct using raw values. + (sim_fpu_is): Differentiate between negative and positive + infinity. + Tue Apr 14 18:49:31 1998 Andrew Cagney * sim-bits.h (EXTEND4): Define. diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c index 99e922c..8931ad3 100644 --- a/sim/common/sim-fpu.c +++ b/sim/common/sim-fpu.c @@ -2,7 +2,7 @@ of the floating point routines in libgcc1.c for targets without hardware floating point. */ -/* Copyright (C) 1994,1997 Free Software Foundation, Inc. +/* Copyright (C) 1994,1997-1998 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the @@ -712,6 +712,40 @@ sim_fpu_to64 (unsigned64 *u, } +INLINE_SIM_FPU (void) +sim_fpu_fractionto (sim_fpu *f, + int sign, + int normal_exp, + unsigned64 fraction, + int precision) +{ + int shift = (NR_FRAC_GUARD - precision); + f->class = sim_fpu_class_number; + f->sign = sign; + f->normal_exp = normal_exp; + /* shift the fraction to where sim-fpu expects it */ + if (shift >= 0) + f->fraction = (fraction << shift); + else + f->fraction = (fraction >> -shift); + f->fraction |= IMPLICIT_1; +} + + +INLINE_SIM_FPU (unsigned64) +sim_fpu_tofraction (const sim_fpu *d, + int precision) +{ + /* we have NR_FRAC_GUARD bits, we want only PRECISION bits */ + int shift = (NR_FRAC_GUARD - precision); + unsigned64 fraction = (d->fraction & ~IMPLICIT_1); + if (shift >= 0) + return fraction >> shift; + else + return fraction << -shift; +} + + /* Rounding */ STATIC_INLINE_SIM_FPU (int) @@ -2186,6 +2220,7 @@ sim_fpu_exp (const sim_fpu *d) } + INLINE_SIM_FPU (int) sim_fpu_is (const sim_fpu *d) { @@ -2196,8 +2231,10 @@ sim_fpu_is (const sim_fpu *d) case sim_fpu_class_snan: return SIM_FPU_IS_SNAN; case sim_fpu_class_infinity: - return SIM_FPU_IS_NINF; - return SIM_FPU_IS_PINF; + if (d->sign) + return SIM_FPU_IS_NINF; + else + return SIM_FPU_IS_PINF; case sim_fpu_class_number: if (d->sign) return SIM_FPU_IS_NNUMBER; diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 82afc31..6a34a66 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,21 @@ +start-sanitize-r5900 +Thu Apr 16 10:40:29 1998 Andrew Cagney + + * r5900.igen (CFC1, CTC1): Implement R5900 specific version. + * mips.igen (CFC1, CTC1): R5900 des not use generic version. + + * r5900.igen (r59fp_unpack): New function. + (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S, + RSQRT.S, SQRT.S): Use. + (r59fp_zero): New function. + (r59fp_overflow): Generate r5900 specific overflow value. + (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow + to zero. + (CVT.S.W, CVT.W.S): Exchange implementations. + + * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile. + +end-sanitize-r5900 start-sanitize-tx19 Thu Apr 16 09:14:44 1998 Andrew Cagney -- 2.7.4