From 7d78614ae9939b7786bad01c653c44c2aa403cc5 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Sat, 29 Oct 2016 01:03:41 +0000 Subject: [PATCH] AArch64DeadRegisterDefinitionsPass: Cleanup; NFC - Fix doxygen file comment - reduce indentation in loop - Factor out some common subexpressions - Move independent helper function out of class - Fix Changed flag (this is not strictly NFC but a bugfix, but the flag seems ignored anyway) llvm-svn: 285488 --- .../AArch64/AArch64DeadRegisterDefinitionsPass.cpp | 107 ++++++++++----------- 1 file changed, 53 insertions(+), 54 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 90fd1ab..389520f 100644 --- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -6,9 +6,9 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// When allowed by the instruction, replace a dead definition of a GPR with -// the zero register. This makes the code a bit friendlier towards the -// hardware's register renamer. +/// \file When allowed by the instruction, replace a dead definition of a GPR +/// with the zero register. This makes the code a bit friendlier towards the +/// hardware's register renamer. //===----------------------------------------------------------------------===// #include "AArch64.h" @@ -32,12 +32,12 @@ namespace { class AArch64DeadRegisterDefinitions : public MachineFunctionPass { private: const TargetRegisterInfo *TRI; + bool Changed; bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI); - bool processMachineBasicBlock(MachineBasicBlock &MBB); - bool usesFrameIndex(const MachineInstr &MI); + void processMachineBasicBlock(MachineBasicBlock &MBB); public: static char ID; // Pass identification, replacement for typeid. - explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) { + AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) { initializeAArch64DeadRegisterDefinitionsPass( *PassRegistry::getPassRegistry()); } @@ -71,16 +71,15 @@ bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg( return false; } -bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) { - for (const MachineOperand &Op : MI.uses()) - if (Op.isFI()) +static bool usesFrameIndex(const MachineInstr &MI) { + for (const MachineOperand &MO : MI.uses()) + if (MO.isFI()) return true; return false; } -bool AArch64DeadRegisterDefinitions::processMachineBasicBlock( +void AArch64DeadRegisterDefinitions::processMachineBasicBlock( MachineBasicBlock &MBB) { - bool Changed = false; for (MachineInstr &MI : MBB) { if (usesFrameIndex(MI)) { // We need to skip this instruction because while it appears to have a @@ -95,62 +94,62 @@ bool AArch64DeadRegisterDefinitions::processMachineBasicBlock( DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n"); continue; } - for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { - MachineOperand &MO = MI.getOperand(i); - if (MO.isReg() && MO.isDead() && MO.isDef()) { - assert(!MO.isImplicit() && "Unexpected implicit def!"); - DEBUG(dbgs() << " Dead def operand #" << i << " in:\n "; - MI.print(dbgs())); - // Be careful not to change the register if it's a tied operand. - if (MI.isRegTiedToUseOperand(i)) { - DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); - continue; - } - // Don't change the register if there's an implicit def of a subreg or - // superreg. - if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) { - DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n"); - continue; - } - // Make sure the instruction take a register class that contains - // the zero register and replace it if so. - unsigned NewReg; - switch (MI.getDesc().OpInfo[i].RegClass) { - default: - DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); - continue; - case AArch64::GPR32RegClassID: - NewReg = AArch64::WZR; - break; - case AArch64::GPR64RegClassID: - NewReg = AArch64::XZR; - break; - } - DEBUG(dbgs() << " Replacing with zero register. New:\n "); - MO.setReg(NewReg); - DEBUG(MI.print(dbgs())); - ++NumDeadDefsReplaced; - // Only replace one dead register, see check for zero register above. + const MCInstrDesc &Desc = MI.getDesc(); + for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { + MachineOperand &MO = MI.getOperand(I); + if (!MO.isReg() || !MO.isDead() || !MO.isDef()) + continue; + assert(!MO.isImplicit() && "Unexpected implicit def!"); + DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; + MI.print(dbgs())); + // Be careful not to change the register if it's a tied operand. + if (MI.isRegTiedToUseOperand(I)) { + DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); + continue; + } + // Don't change the register if there's an implicit def of a subreg or + // superreg. + if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) { + DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n"); + continue; + } + // Make sure the instruction take a register class that contains + // the zero register and replace it if so. + unsigned NewReg; + switch (Desc.OpInfo[I].RegClass) { + default: + DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); + continue; + case AArch64::GPR32RegClassID: + NewReg = AArch64::WZR; + break; + case AArch64::GPR64RegClassID: + NewReg = AArch64::XZR; break; } + DEBUG(dbgs() << " Replacing with zero register. New:\n "); + MO.setReg(NewReg); + DEBUG(MI.print(dbgs())); + ++NumDeadDefsReplaced; + Changed = true; + // Only replace one dead register, see check for zero register above. + break; } } - return Changed; } // Scan the function for instructions that have a dead definition of a // register. Replace that register with the zero register when possible. bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { - TRI = MF.getSubtarget().getRegisterInfo(); - bool Changed = false; - DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); - if (skipFunction(*MF.getFunction())) return false; + TRI = MF.getSubtarget().getRegisterInfo(); + bool Changed = false; + DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); + Changed = false; for (auto &MBB : MF) - if (processMachineBasicBlock(MBB)) - Changed = true; + processMachineBasicBlock(MBB); return Changed; } -- 2.7.4