From 7d010731e8bd5c4346b939a313a3ec68956130b7 Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Tue, 7 Feb 2023 14:48:05 +0800 Subject: [PATCH] RISC-V: Add vwmul.v C++ api TETS gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwmul_vv-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwmul_vv-1.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv-2.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv-3.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tum-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tum-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tum-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-1.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-2.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-3.C | 216 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tum-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tum-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tum-3.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C | 111 +++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C | 111 +++++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C new file mode 100644 index 0000000..975cadd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C new file mode 100644 index 0000000..e93ca69 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C new file mode 100644 index 0000000..d55c1af --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C new file mode 100644 index 0000000..a54a541 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C new file mode 100644 index 0000000..e9ad592 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C new file mode 100644 index 0000000..706ae97 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C new file mode 100644 index 0000000..e9483dc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C new file mode 100644 index 0000000..35f0102 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C new file mode 100644 index 0000000..bc5b27b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C new file mode 100644 index 0000000..105d91c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C new file mode 100644 index 0000000..c2cdde3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C new file mode 100644 index 0000000..b6945ec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C new file mode 100644 index 0000000..1c50f12 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C new file mode 100644 index 0000000..c8c9677 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C new file mode 100644 index 0000000..8919583 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C new file mode 100644 index 0000000..e4f10fa --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C new file mode 100644 index 0000000..dc64a10 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C new file mode 100644 index 0000000..2978e23 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C new file mode 100644 index 0000000..42572b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C new file mode 100644 index 0000000..fe3caef --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C new file mode 100644 index 0000000..ac960f3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C new file mode 100644 index 0000000..72da245 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C new file mode 100644 index 0000000..a3dca75 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C new file mode 100644 index 0000000..40748cd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C new file mode 100644 index 0000000..10ee63a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C new file mode 100644 index 0000000..138b822 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C new file mode 100644 index 0000000..137e934 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C new file mode 100644 index 0000000..92ab475 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C new file mode 100644 index 0000000..30877b6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C new file mode 100644 index 0000000..d1efd5a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ -- 2.7.4