From 7cdf4326a8f290da3804cc92b9dccf45195079dc Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 18 Jun 2020 18:20:58 +0100 Subject: [PATCH] [LiveIntervals] Fix early-clobber handling in handleMoveUp Without this fix, handleMoveUp can create an invalid live range like this: [98904e,98908r:0)[98908e,227504r:1) where the two segments overlap, but only because we have lost the "e" (early-clobber) on the end point of the first segment. Differential Revision: https://reviews.llvm.org/D82110 --- llvm/lib/CodeGen/LiveIntervals.cpp | 2 +- llvm/unittests/MI/LiveIntervalTest.cpp | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp index b830c93..2bbe036 100644 --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -1342,7 +1342,7 @@ private: OldIdxOut->start = NewIdxDef; OldIdxVNI->def = NewIdxDef; if (OldIdxIn != E && SlotIndex::isEarlierInstr(NewIdx, OldIdxIn->end)) - OldIdxIn->end = NewIdx.getRegSlot(); + OldIdxIn->end = NewIdxDef; } } else if (OldIdxIn != E && SlotIndex::isEarlierInstr(NewIdxOut->start, NewIdx) diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp index ea8476d..5c974ea 100644 --- a/llvm/unittests/MI/LiveIntervalTest.cpp +++ b/llvm/unittests/MI/LiveIntervalTest.cpp @@ -443,6 +443,21 @@ TEST(LiveIntervalTest, DeadSubRegMoveUp) { }); } +TEST(LiveIntervalTest, EarlyClobberSubRegMoveUp) { + // handleMoveUp had a bug where moving an early-clobber subreg def into the + // middle of an earlier segment resulted in an invalid live range. + liveIntervalTest(R"MIR( + %4:sreg_32 = IMPLICIT_DEF + %6:sreg_32 = IMPLICIT_DEF + undef early-clobber %9.sub0:sreg_64 = WWM %4:sreg_32, implicit $exec + %5:sreg_32 = S_FLBIT_I32_B32 %9.sub0:sreg_64 + early-clobber %9.sub1:sreg_64 = WWM %6:sreg_32, implicit $exec + %7:sreg_32 = S_FLBIT_I32_B32 %9.sub1:sreg_64 +)MIR", [](MachineFunction &MF, LiveIntervals &LIS) { + testHandleMove(MF, LIS, 4, 3); + }); +} + TEST(LiveIntervalTest, TestMoveSubRegDefAcrossUseDef) { liveIntervalTest(R"MIR( %1:vreg_64 = IMPLICIT_DEF -- 2.7.4