From 7c72ba5c91f040eeff249b36525262ad75bbf1d0 Mon Sep 17 00:00:00 2001
From: Dong-Heon Jung <clamp03@gmail.com>
Date: Wed, 17 May 2023 22:09:41 +0900
Subject: [PATCH] [RISC-V][JIT] Fix floating-point args passing (#86244)

---
 src/coreclr/jit/codegenriscv64.cpp |  9 ++++++++-
 src/coreclr/jit/emitriscv64.cpp    | 14 ++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp
index b68929e..eb6ed52 100644
--- a/src/coreclr/jit/codegenriscv64.cpp
+++ b/src/coreclr/jit/codegenriscv64.cpp
@@ -5141,8 +5141,15 @@ void CodeGen::genPutArgReg(GenTreeOp* tree)
     GenTree* op1 = tree->gtOp1;
     genConsumeReg(op1);
 
+    if (varTypeIsFloating(tree) && emitter::isGeneralRegister(targetReg))
+    {
+        // Pass the float args by integer register
+        targetType = emitActualTypeSize(targetType) == EA_4BYTE ? TYP_INT : TYP_LONG;
+    }
+
     // If child node is not already in the register we need, move it
-    GetEmitter()->emitIns_Mov(ins_Copy(targetType), emitActualTypeSize(targetType), targetReg, op1->GetRegNum(), true);
+    GetEmitter()->emitIns_Mov(ins_Copy(op1->GetRegNum(), targetType), emitActualTypeSize(targetType), targetReg,
+                              op1->GetRegNum(), true);
     genProduceReg(tree);
 }
 
diff --git a/src/coreclr/jit/emitriscv64.cpp b/src/coreclr/jit/emitriscv64.cpp
index 1dbe97a..3740534 100644
--- a/src/coreclr/jit/emitriscv64.cpp
+++ b/src/coreclr/jit/emitriscv64.cpp
@@ -541,13 +541,27 @@ void emitter::emitIns_Mov(
     if (!canSkip || (dstReg != srcReg))
     {
         if ((EA_4BYTE == attr) && (INS_mov == ins))
+        {
+            assert(isGeneralRegisterOrR0(srcReg));
+            assert(isGeneralRegisterOrR0(dstReg));
             emitIns_R_R_I(INS_addiw, attr, dstReg, srcReg, 0);
+        }
         else if (INS_fsgnj_s == ins || INS_fsgnj_d == ins)
+        {
+            assert(isFloatReg(srcReg));
+            assert(isFloatReg(dstReg));
             emitIns_R_R_R(ins, attr, dstReg, srcReg, srcReg);
+        }
         else if (genIsValidFloatReg(srcReg) || genIsValidFloatReg(dstReg))
+        {
             emitIns_R_R(ins, attr, dstReg, srcReg);
+        }
         else
+        {
+            assert(isGeneralRegisterOrR0(srcReg));
+            assert(isGeneralRegisterOrR0(dstReg));
             emitIns_R_R_I(INS_addi, attr, dstReg, srcReg, 0);
+        }
     }
 }
 
-- 
2.7.4