From 7c1ac11c1e6de5713d6ffeb2cf6c26c65afadf4a Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Thu, 21 Apr 2022 15:58:44 +0800 Subject: [PATCH] hw_random: starfive-trng: Use stardand clock and reset apis for initialization Signed-off-by: Hal Feng --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 ++- drivers/char/hw_random/starfive-trng.c | 54 ++++++++++++++++++++++++++------ 2 files changed, 48 insertions(+), 11 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index dcea9bd..8e7686f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -489,7 +489,10 @@ trng: trng@1600C000 { compatible = "starfive,trng"; reg = <0x0 0x1600C000 0x0 0x4000>; - clocks = <&apb12clk>; + clocks = <&clkgen JH7110_SEC_HCLK>, + <&clkgen JH7110_SEC_MISCAHB_CLK>; + clock-names = "hclk", "miscahb_clk"; + resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>; interrupts = <30>; status = "disabled"; }; diff --git a/drivers/char/hw_random/starfive-trng.c b/drivers/char/hw_random/starfive-trng.c index cd50543..f760c9d 100644 --- a/drivers/char/hw_random/starfive-trng.c +++ b/drivers/char/hw_random/starfive-trng.c @@ -1,13 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - ****************************************************************************** - * @file starfive-trng.c - * @author StarFive Technology - * @version V1.0 - * @date 09/08/2021 - * @brief - ****************************************************************************** - * @copy + * Copyright (C) 2021 StarFive, Inc * * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE @@ -15,8 +8,6 @@ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd. */ #include @@ -29,6 +20,8 @@ #include #include #include +#include +#include #include "starfive-trng.h" @@ -37,6 +30,9 @@ struct trng { struct device *dev; void __iomem *base; + struct clk *hclk; + struct clk *miscahb_clk; + struct reset_control *rst; u32 mode; u32 ctl_cmd; u32 test_mode; @@ -312,6 +308,44 @@ static int trng_probe(struct platform_device *pdev) return ret; } + rng->hclk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(rng->hclk)) { + ret = PTR_ERR(rng->hclk); + dev_err(&pdev->dev, + "Failed to get the trng hclk clock, %d\n", ret); + return ret; + } + rng->miscahb_clk = devm_clk_get(&pdev->dev, "miscahb_clk"); + if (IS_ERR(rng->miscahb_clk)) { + ret = PTR_ERR(rng->miscahb_clk); + dev_err(&pdev->dev, + "Failed to get the trng miscahb_clk clock, %d\n", ret); + return ret; + } + + rng->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(rng->rst)) { + ret = PTR_ERR(rng->rst); + dev_err(&pdev->dev, + "Failed to get the sec_top reset, %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(rng->hclk); + if (ret) { + dev_err(&pdev->dev, + "Failed to enable the trng hclk clock, %d\n", ret); + return ret; + } + ret = clk_prepare_enable(rng->miscahb_clk); + if (ret) { + dev_err(&pdev->dev, + "Failed to enable the trng miscahb_clk clock, %d\n", ret); + return ret; + } + + reset_control_deassert(rng->rst); + rng->rng.name = pdev->name; rng->rng.init = trng_init; rng->rng.cleanup = trng_cleanup; -- 2.7.4