From 7c1a6873aa53b11605e8860b0ae3ff11bb6e9a02 Mon Sep 17 00:00:00 2001 From: David Green Date: Sat, 28 Mar 2020 16:11:37 +0000 Subject: [PATCH] [ARM] VMOV.64 immediate tests. NFC --- llvm/test/CodeGen/Thumb2/mve-vmovimm.ll | 797 +++++++++++++++++++++++++------- 1 file changed, 638 insertions(+), 159 deletions(-) diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll index 94721a5..640aabc 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll @@ -1,286 +1,765 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE +; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE +; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() { -; CHECK-LABEL: mov_int8_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q0, #0x1 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int8_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i8 q0, #0x1 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int8_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i8 q1, #0x1 +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <16 x i8> } define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() { -; CHECK-LABEL: mov_int8_m1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q0, #0xff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int8_m1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i8 q0, #0xff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int8_m1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i8 q1, #0xff +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <16 x i8> } define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() { -; CHECK-LABEL: mov_int16_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i16 q0, #0x1 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int16_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i16 q0, #0x1 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int16_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i16 q1, #0x1 +; CHECKBE-NEXT: vrev64.16 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <8 x i16> } define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() { -; CHECK-LABEL: mov_int16_m1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q0, #0xff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int16_m1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i8 q0, #0xff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int16_m1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i8 q1, #0xff +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <8 x i16> } define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() { -; CHECK-LABEL: mov_int16_256: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i16 q0, #0x100 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int16_256: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i16 q0, #0x100 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int16_256: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i16 q1, #0x100 +; CHECKBE-NEXT: vrev64.16 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <8 x i16> } define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() { -; CHECK-LABEL: mov_int16_257: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q0, #0x1 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int16_257: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i8 q0, #0x1 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int16_257: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i8 q1, #0x1 +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <8 x i16> } define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() { -; CHECK-LABEL: mov_int16_258: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI6_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI6_0: -; CHECK-NEXT: .long 16908546 @ double 8.204306265173532E-304 -; CHECK-NEXT: .long 16908546 -; CHECK-NEXT: .long 16908546 @ double 8.204306265173532E-304 -; CHECK-NEXT: .long 16908546 +; CHECKLE-LABEL: mov_int16_258: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI6_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI6_0: +; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304 +; CHECKLE-NEXT: .long 16908546 +; CHECKLE-NEXT: .long 16908546 @ double 8.204306265173532E-304 +; CHECKLE-NEXT: .long 16908546 +; +; CHECKBE-LABEL: mov_int16_258: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI6_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI6_0: +; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304 +; CHECKBE-NEXT: .long 16908546 +; CHECKBE-NEXT: .long 16908546 @ double 8.204306265173532E-304 +; CHECKBE-NEXT: .long 16908546 entry: ret <8 x i16> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() { -; CHECK-LABEL: mov_int32_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q0, #0x1 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i32 q0, #0x1 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i32 q1, #0x1 +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() { -; CHECK-LABEL: mov_int32_256: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q0, #0x100 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_256: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i32 q0, #0x100 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_256: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i32 q1, #0x100 +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() { -; CHECK-LABEL: mov_int32_65536: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q0, #0x10000 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_65536: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i32 q0, #0x10000 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_65536: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i32 q1, #0x10000 +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() { -; CHECK-LABEL: mov_int32_16777216: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q0, #0x1000000 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_16777216: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i32 q0, #0x1000000 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_16777216: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i32 q1, #0x1000000 +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() { -; CHECK-LABEL: mov_int32_16777217: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI11_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI11_0: -; CHECK-NEXT: .long 16777217 @ double 7.2911290000737531E-304 -; CHECK-NEXT: .long 16777217 -; CHECK-NEXT: .long 16777217 @ double 7.2911290000737531E-304 -; CHECK-NEXT: .long 16777217 +; CHECKLE-LABEL: mov_int32_16777217: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI11_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI11_0: +; CHECKLE-NEXT: .long 16777217 @ double 7.2911290000737531E-304 +; CHECKLE-NEXT: .long 16777217 +; CHECKLE-NEXT: .long 16777217 @ double 7.2911290000737531E-304 +; CHECKLE-NEXT: .long 16777217 +; +; CHECKBE-LABEL: mov_int32_16777217: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI11_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI11_0: +; CHECKBE-NEXT: .long 16777217 @ double 7.2911290000737531E-304 +; CHECKBE-NEXT: .long 16777217 +; CHECKBE-NEXT: .long 16777217 @ double 7.2911290000737531E-304 +; CHECKBE-NEXT: .long 16777217 entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() { -; CHECK-LABEL: mov_int32_17919: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q0, #0x45ff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_17919: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i32 q0, #0x45ff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_17919: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i32 q1, #0x45ff +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() { -; CHECK-LABEL: mov_int32_4587519: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q0, #0x45ffff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_4587519: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i32 q0, #0x45ffff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_4587519: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i32 q1, #0x45ffff +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() { -; CHECK-LABEL: mov_int32_m1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q0, #0xff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_m1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i8 q0, #0xff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_m1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i8 q1, #0xff +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() { -; CHECK-LABEL: mov_int32_4294901760: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmvn.i32 q0, #0xffff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_4294901760: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmvn.i32 q0, #0xffff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_4294901760: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmvn.i32 q1, #0xffff +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() { -; CHECK-LABEL: mov_int32_4278190335: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI16_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI16_0: -; CHECK-NEXT: .long 4278190335 @ double -5.4874634341155774E+303 -; CHECK-NEXT: .long 4278190335 -; CHECK-NEXT: .long 4278190335 @ double -5.4874634341155774E+303 -; CHECK-NEXT: .long 4278190335 +; CHECKLE-LABEL: mov_int32_4278190335: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI16_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI16_0: +; CHECKLE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303 +; CHECKLE-NEXT: .long 4278190335 +; CHECKLE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303 +; CHECKLE-NEXT: .long 4278190335 +; +; CHECKBE-LABEL: mov_int32_4278190335: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI16_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI16_0: +; CHECKBE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303 +; CHECKBE-NEXT: .long 4278190335 +; CHECKBE-NEXT: .long 4278190335 @ double -5.4874634341155774E+303 +; CHECKBE-NEXT: .long 4278190335 entry: ret <4 x i32> } define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() { -; CHECK-LABEL: mov_int32_4278255615: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmvn.i32 q0, #0xff0000 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int32_4278255615: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmvn.i32 q0, #0xff0000 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int32_4278255615: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmvn.i32 q1, #0xff0000 +; CHECKBE-NEXT: vrev64.32 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <4 x i32> } define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() { -; CHECK-LABEL: mov_int64_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI18_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI18_0: -; CHECK-NEXT: .long 1 @ double 4.9406564584124654E-324 -; CHECK-NEXT: .long 0 -; CHECK-NEXT: .long 1 @ double 4.9406564584124654E-324 -; CHECK-NEXT: .long 0 +; CHECKLE-LABEL: mov_int64_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI18_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI18_0: +; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324 +; CHECKLE-NEXT: .long 0 +; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324 +; CHECKLE-NEXT: .long 0 +; +; CHECKBE-LABEL: mov_int64_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI18_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI18_0: +; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324 +; CHECKBE-NEXT: .long 1 +; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324 +; CHECKBE-NEXT: .long 1 entry: ret <2 x i64> } +define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() { +; CHECKLE-LABEL: mov_int64_ff: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI19_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI19_0: +; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321 +; CHECKLE-NEXT: .long 0 +; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321 +; CHECKLE-NEXT: .long 0 +; +; CHECKBE-LABEL: mov_int64_ff: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI19_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI19_0: +; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321 +; CHECKBE-NEXT: .long 255 +; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321 +; CHECKBE-NEXT: .long 255 +entry: + ret <2 x i64> < i64 255, i64 255 > +} + define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() { -; CHECK-LABEL: mov_int64_m1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q0, #0xff -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_int64_m1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i8 q0, #0xff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int64_m1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i8 q1, #0xff +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +entry: + ret <2 x i64> < i64 -1, i64 -1 > +} + +define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() { +; CHECKLE-LABEL: mov_int64_ff0000ff0000ffff: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI21_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI21_0: +; CHECKLE-NEXT: .long 65535 @ double -5.4874582226568829E+303 +; CHECKLE-NEXT: .long 4278190335 +; CHECKLE-NEXT: .long 65535 @ double -5.4874582226568829E+303 +; CHECKLE-NEXT: .long 4278190335 +; +; CHECKBE-LABEL: mov_int64_ff0000ff0000ffff: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI21_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI21_0: +; CHECKBE-NEXT: .long 4278190335 @ double -5.4874582226568829E+303 +; CHECKBE-NEXT: .long 65535 +; CHECKBE-NEXT: .long 4278190335 @ double -5.4874582226568829E+303 +; CHECKBE-NEXT: .long 65535 +entry: + ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > +} + +define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() { +; CHECKLE-LABEL: mov_int64_f_0: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI22_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI22_0: +; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321 +; CHECKLE-NEXT: .long 0 +; CHECKLE-NEXT: .long 0 @ double 0 +; CHECKLE-NEXT: .long 0 +; +; CHECKBE-LABEL: mov_int64_f_0: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI22_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI22_0: +; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321 +; CHECKBE-NEXT: .long 255 +; CHECKBE-NEXT: .long 0 @ double 0 +; CHECKBE-NEXT: .long 0 +entry: + ret <2 x i64> < i64 255, i64 0 > +} + +define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() { +; CHECKLE-LABEL: mov_int64_0f000f0f: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI23_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI23_0: +; CHECKLE-NEXT: .long 16711935 @ double 7.0632744699731897E-304 +; CHECKLE-NEXT: .long 16711680 +; CHECKLE-NEXT: .long 16711935 @ double 7.0632744699731897E-304 +; CHECKLE-NEXT: .long 16711680 +; +; CHECKBE-LABEL: mov_int64_0f000f0f: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI23_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI23_0: +; CHECKBE-NEXT: .long 4278255360 @ double -5.8276674374138332E+303 +; CHECKBE-NEXT: .long 65280 +; CHECKBE-NEXT: .long 4278255360 @ double -5.8276674374138332E+303 +; CHECKBE-NEXT: .long 65280 entry: - ret <2 x i64> + ret <16 x i8> +} + +define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() { +; CHECKLE-LABEL: mov_int64_ff00ffff: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI24_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI24_0: +; CHECKLE-NEXT: .long 65535 @ double NaN +; CHECKLE-NEXT: .long 4294967295 +; CHECKLE-NEXT: .long 65535 @ double NaN +; CHECKLE-NEXT: .long 4294967295 +; +; CHECKBE-LABEL: mov_int64_ff00ffff: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI24_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI24_0: +; CHECKBE-NEXT: .long 4294901760 @ double NaN +; CHECKBE-NEXT: .long 4294967295 +; CHECKBE-NEXT: .long 4294901760 @ double NaN +; CHECKBE-NEXT: .long 4294967295 +entry: + ret <8 x i16> +} + +define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() { +; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i16 q0, #0xff +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_int64_0f0f0f0f0f0f0f0f: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i16 q1, #0xff00 +; CHECKBE-NEXT: vrev64.16 q0, q1 +; CHECKBE-NEXT: bx lr +entry: + ret <16 x i8> } define arm_aapcs_vfpcc <4 x float> @mov_float_1() { -; CHECK-LABEL: mov_float_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI20_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI20_0: -; CHECK-NEXT: .long 1065353216 @ double 0.007812501848093234 -; CHECK-NEXT: .long 1065353216 -; CHECK-NEXT: .long 1065353216 @ double 0.007812501848093234 -; CHECK-NEXT: .long 1065353216 +; CHECKLE-LABEL: mov_float_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI26_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI26_0: +; CHECKLE-NEXT: .long 1065353216 @ double 0.007812501848093234 +; CHECKLE-NEXT: .long 1065353216 +; CHECKLE-NEXT: .long 1065353216 @ double 0.007812501848093234 +; CHECKLE-NEXT: .long 1065353216 +; +; CHECKBE-LABEL: mov_float_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI26_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI26_0: +; CHECKBE-NEXT: .long 1065353216 @ double 0.007812501848093234 +; CHECKBE-NEXT: .long 1065353216 +; CHECKBE-NEXT: .long 1065353216 @ double 0.007812501848093234 +; CHECKBE-NEXT: .long 1065353216 entry: ret <4 x float> } define arm_aapcs_vfpcc <4 x float> @mov_float_m3() { -; CHECK-LABEL: mov_float_m3: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI21_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI21_0: -; CHECK-NEXT: .long 3225419776 @ double -32.000022917985916 -; CHECK-NEXT: .long 3225419776 -; CHECK-NEXT: .long 3225419776 @ double -32.000022917985916 -; CHECK-NEXT: .long 3225419776 +; CHECKLE-LABEL: mov_float_m3: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI27_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI27_0: +; CHECKLE-NEXT: .long 3225419776 @ double -32.000022917985916 +; CHECKLE-NEXT: .long 3225419776 +; CHECKLE-NEXT: .long 3225419776 @ double -32.000022917985916 +; CHECKLE-NEXT: .long 3225419776 +; +; CHECKBE-LABEL: mov_float_m3: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI27_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI27_0: +; CHECKBE-NEXT: .long 3225419776 @ double -32.000022917985916 +; CHECKBE-NEXT: .long 3225419776 +; CHECKBE-NEXT: .long 3225419776 @ double -32.000022917985916 +; CHECKBE-NEXT: .long 3225419776 entry: ret <4 x float> } define arm_aapcs_vfpcc <8 x half> @mov_float16_1() { -; CHECK-LABEL: mov_float16_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i16 q0, #0x3c00 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_float16_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i16 q0, #0x3c00 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_float16_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i16 q1, #0x3c00 +; CHECKBE-NEXT: vrev64.16 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <8 x half> } define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() { -; CHECK-LABEL: mov_float16_m3: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i16 q0, #0xc200 -; CHECK-NEXT: bx lr +; CHECKLE-LABEL: mov_float16_m3: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: vmov.i16 q0, #0xc200 +; CHECKLE-NEXT: bx lr +; +; CHECKBE-LABEL: mov_float16_m3: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: vmov.i16 q1, #0xc200 +; CHECKBE-NEXT: vrev64.16 q0, q1 +; CHECKBE-NEXT: bx lr entry: ret <8 x half> } define arm_aapcs_vfpcc <2 x double> @mov_double_1() { -; CHECK-LABEL: mov_double_1: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: adr r0, .LCPI24_0 -; CHECK-NEXT: vldrw.u32 q0, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.1: -; CHECK-NEXT: .LCPI24_0: -; CHECK-NEXT: .long 0 @ double 1 -; CHECK-NEXT: .long 1072693248 -; CHECK-NEXT: .long 0 @ double 1 -; CHECK-NEXT: .long 1072693248 +; CHECKLE-LABEL: mov_double_1: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI30_0 +; CHECKLE-NEXT: vldrw.u32 q0, [r0] +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI30_0: +; CHECKLE-NEXT: .long 0 @ double 1 +; CHECKLE-NEXT: .long 1072693248 +; CHECKLE-NEXT: .long 0 @ double 1 +; CHECKLE-NEXT: .long 1072693248 +; +; CHECKBE-LABEL: mov_double_1: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI30_0 +; CHECKBE-NEXT: vldrb.u8 q1, [r0] +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI30_0: +; CHECKBE-NEXT: .long 1072693248 @ double 1 +; CHECKBE-NEXT: .long 0 +; CHECKBE-NEXT: .long 1072693248 @ double 1 +; CHECKBE-NEXT: .long 0 entry: ret <2 x double> } + +define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) { +; CHECKLE-LABEL: test: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI31_0 +; CHECKLE-NEXT: vldrw.u32 q1, [r0] +; CHECKLE-NEXT: vorr q0, q0, q1 +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI31_0: +; CHECKLE-NEXT: .byte 255 @ 0xff +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 255 @ 0xff +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 255 @ 0xff +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 255 @ 0xff +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 255 @ 0xff +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 0 @ 0x0 +; CHECKLE-NEXT: .byte 255 @ 0xff +; CHECKLE-NEXT: .byte 0 @ 0x0 +; +; CHECKBE-LABEL: test: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI31_0 +; CHECKBE-NEXT: vrev64.8 q1, q0 +; CHECKBE-NEXT: vldrb.u8 q0, [r0] +; CHECKBE-NEXT: vorr q1, q1, q0 +; CHECKBE-NEXT: vrev64.8 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI31_0: +; CHECKBE-NEXT: .byte 255 @ 0xff +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 255 @ 0xff +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 255 @ 0xff +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 255 @ 0xff +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 255 @ 0xff +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 0 @ 0x0 +; CHECKBE-NEXT: .byte 255 @ 0xff +; CHECKBE-NEXT: .byte 0 @ 0x0 +entry: + %o = or <16 x i8> %i, + ret <16 x i8> %o +} + +define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) { +; CHECKLE-LABEL: test2: +; CHECKLE: @ %bb.0: @ %entry +; CHECKLE-NEXT: adr r0, .LCPI32_0 +; CHECKLE-NEXT: vldrw.u32 q1, [r0] +; CHECKLE-NEXT: vorr q0, q0, q1 +; CHECKLE-NEXT: bx lr +; CHECKLE-NEXT: .p2align 4 +; CHECKLE-NEXT: @ %bb.1: +; CHECKLE-NEXT: .LCPI32_0: +; CHECKLE-NEXT: .short 65535 @ 0xffff +; CHECKLE-NEXT: .short 0 @ 0x0 +; CHECKLE-NEXT: .short 65535 @ 0xffff +; CHECKLE-NEXT: .short 65535 @ 0xffff +; CHECKLE-NEXT: .short 65535 @ 0xffff +; CHECKLE-NEXT: .short 0 @ 0x0 +; CHECKLE-NEXT: .short 65535 @ 0xffff +; CHECKLE-NEXT: .short 65535 @ 0xffff +; +; CHECKBE-LABEL: test2: +; CHECKBE: @ %bb.0: @ %entry +; CHECKBE-NEXT: adr r0, .LCPI32_0 +; CHECKBE-NEXT: vrev64.16 q1, q0 +; CHECKBE-NEXT: vldrh.u16 q0, [r0] +; CHECKBE-NEXT: vorr q1, q1, q0 +; CHECKBE-NEXT: vrev64.16 q0, q1 +; CHECKBE-NEXT: bx lr +; CHECKBE-NEXT: .p2align 4 +; CHECKBE-NEXT: @ %bb.1: +; CHECKBE-NEXT: .LCPI32_0: +; CHECKBE-NEXT: .short 65535 @ 0xffff +; CHECKBE-NEXT: .short 0 @ 0x0 +; CHECKBE-NEXT: .short 65535 @ 0xffff +; CHECKBE-NEXT: .short 65535 @ 0xffff +; CHECKBE-NEXT: .short 65535 @ 0xffff +; CHECKBE-NEXT: .short 0 @ 0x0 +; CHECKBE-NEXT: .short 65535 @ 0xffff +; CHECKBE-NEXT: .short 65535 @ 0xffff +entry: + %o = or <8 x i16> %i, + ret <8 x i16> %o +} -- 2.7.4