From 7b3d162fba795b6db258ab835b43953e59629478 Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Tue, 20 Mar 2018 12:58:34 +0000 Subject: [PATCH] [llvm-mca] Use llvm::make_unique in a few places. NFC Also, clang-format a couple of DEBUG functions. llvm-svn: 327978 --- llvm/tools/llvm-mca/Backend.cpp | 5 ++--- llvm/tools/llvm-mca/InstrBuilder.cpp | 30 +++++++++++++----------------- llvm/tools/llvm-mca/InstrBuilder.h | 3 ++- llvm/tools/llvm-mca/Instruction.h | 4 ++-- 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/llvm/tools/llvm-mca/Backend.cpp b/llvm/tools/llvm-mca/Backend.cpp index 8d34175..cad7db3 100644 --- a/llvm/tools/llvm-mca/Backend.cpp +++ b/llvm/tools/llvm-mca/Backend.cpp @@ -33,8 +33,8 @@ void Backend::runCycle(unsigned Cycle) { while (SM.hasNext()) { InstRef IR = SM.peekNext(); - std::unique_ptr NewIS( - IB->createInstruction(IR.first, *IR.second)); + std::unique_ptr NewIS = + IB->createInstruction(IR.first, *IR.second); const InstrDesc &Desc = NewIS->getDesc(); if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(IR.first, *NewIS)) @@ -80,5 +80,4 @@ void Backend::notifyCycleEnd(unsigned Cycle) { for (HWEventListener *Listener : Listeners) Listener->onCycleEnd(Cycle); } - } // namespace mca. diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp index 1bf2b36..82b5f16 100644 --- a/llvm/tools/llvm-mca/InstrBuilder.cpp +++ b/llvm/tools/llvm-mca/InstrBuilder.cpp @@ -112,12 +112,12 @@ initializeUsedResources(InstrDesc &ID, const MCSchedClassDesc &SCDesc, } } - DEBUG( + DEBUG({ for (const std::pair &R : ID.Resources) dbgs() << "\t\tMask=" << R.first << ", cy=" << R.second.size() << '\n'; for (const uint64_t R : ID.Buffers) dbgs() << "\t\tBuffer Mask=" << R << '\n'; - ); + }); } static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc, @@ -260,11 +260,10 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI, } Write.FullyUpdatesSuperRegs = FullyUpdatesSuperRegisters; Write.IsOptionalDef = false; - DEBUG( - dbgs() << "\t\tOpIdx=" << Write.OpIndex - << ", Latency=" << Write.Latency << ", WriteResourceID=" - << Write.SClassOrWriteResourceID << '\n'; - ); + DEBUG({ + dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency + << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n'; + }); CurrentDef++; } @@ -371,7 +370,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) { *SM.getSchedClassDesc(MCDesc.getSchedClass()); // Create a new empty descriptor. - InstrDesc *ID = new InstrDesc(); + std::unique_ptr ID = llvm::make_unique(); if (SCDesc.isVariant()) { errs() << "warning: don't know how to model variant opcodes.\n" @@ -406,7 +405,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) { DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n'); // Now add the new descriptor. - Descriptors[Opcode] = std::unique_ptr(ID); + Descriptors[Opcode] = std::move(ID); } const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) { @@ -416,9 +415,10 @@ const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) { return *Descriptors[MCI.getOpcode()].get(); } -Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) { +std::unique_ptr +InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) { const InstrDesc &D = getOrCreateInstrDesc(MCI); - Instruction *NewIS = new Instruction(D); + std::unique_ptr NewIS = llvm::make_unique(D); // Populate Reads first. for (const ReadDescriptor &RD : D.Reads) { @@ -441,8 +441,7 @@ Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) { // Okay, this is a register operand. Create a ReadState for it. assert(RegID > 0 && "Invalid register ID found!"); - ReadState *NewRDS = new ReadState(RD, RegID); - NewIS->getUses().emplace_back(std::unique_ptr(NewRDS)); + NewIS->getUses().emplace_back(llvm::make_unique(RD, RegID)); } // Now populate writes. @@ -455,12 +454,9 @@ Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) { if (WD.IsOptionalDef && !RegID) continue; - WriteState *NewWS = new WriteState(WD); - NewIS->getDefs().emplace_back(std::unique_ptr(NewWS)); - NewWS->setRegisterID(RegID); + NewIS->getDefs().emplace_back(llvm::make_unique(WD, RegID)); } return NewIS; } - } // namespace mca diff --git a/llvm/tools/llvm-mca/InstrBuilder.h b/llvm/tools/llvm-mca/InstrBuilder.h index a26b846..d31ccef 100644 --- a/llvm/tools/llvm-mca/InstrBuilder.h +++ b/llvm/tools/llvm-mca/InstrBuilder.h @@ -53,7 +53,8 @@ public: const InstrDesc &getOrCreateInstrDesc(const llvm::MCInst &MCI); - Instruction *createInstruction(unsigned Idx, const llvm::MCInst &MCI); + std::unique_ptr createInstruction(unsigned Idx, + const llvm::MCInst &MCI); }; } // namespace mca diff --git a/llvm/tools/llvm-mca/Instruction.h b/llvm/tools/llvm-mca/Instruction.h index a760193..a87420d 100644 --- a/llvm/tools/llvm-mca/Instruction.h +++ b/llvm/tools/llvm-mca/Instruction.h @@ -102,8 +102,8 @@ class WriteState { std::set> Users; public: - WriteState(const WriteDescriptor &Desc) - : WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(Desc.RegisterID) {} + WriteState(const WriteDescriptor &Desc, unsigned RegID) + : WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID) {} WriteState(const WriteState &Other) = delete; WriteState &operator=(const WriteState &Other) = delete; -- 2.7.4