From 7b1cd42745480867c3cea144595b76914eca7d6a Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Wed, 5 Feb 2014 20:15:57 +0000 Subject: [PATCH] altivec.md (altivec_vsum2sws): Adjust code generation for -maltivec=be. gcc: 2014-02-05 Bill Schmidt * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code generation for -maltivec=be. (altivec_vsumsws): Simplify redundant test. gcc/testsuite: 2014-02-05 Bill Schmidt * gcc.dg/vmx/sum2s.c: New. * gcc.dg/vmx/sum2s-be-order.c: New. From-SVN: r207521 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/altivec.md | 24 +++++++++++++++++++----- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c | 19 +++++++++++++++++++ gcc/testsuite/gcc.dg/vmx/sum2s.c | 13 +++++++++++++ 5 files changed, 62 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c create mode 100644 gcc/testsuite/gcc.dg/vmx/sum2s.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d11ae4..8bfc47a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2014-02-05 Bill Schmidt + * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code + generation for -maltivec=be. + (altivec_vsumsws): Simplify redundant test. + +2014-02-05 Bill Schmidt + * altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec. (UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise. (UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 6d78988..c6d5eae 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1605,15 +1605,29 @@ "vsum4ss %0,%1,%2" [(set_attr "type" "veccomplex")]) +;; FIXME: For the following two patterns, the scratch should only be +;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should +;; be emitted separately. (define_insn "altivec_vsum2sws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM2SWS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) + (clobber (match_scratch:V4SI 3 "=v"))] "TARGET_ALTIVEC" - "vsum2sws %0,%1,%2" - [(set_attr "type" "veccomplex")]) +{ + if (VECTOR_ELT_ORDER_BIG) + return "vsum2sws %0,%1,%2"; + else + return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4"; +} + [(set_attr "type" "veccomplex") + (set (attr "length") + (if_then_else + (match_test "VECTOR_ELT_ORDER_BIG") + (const_string "4") + (const_string "12")))]) (define_insn "altivec_vsumsws" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -1624,7 +1638,7 @@ (clobber (match_scratch:V4SI 3 "=v"))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN || VECTOR_ELT_ORDER_BIG) + if (VECTOR_ELT_ORDER_BIG) return "vsumsws %0,%1,%2"; else return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvspltw %0,%3,3"; @@ -1632,7 +1646,7 @@ [(set_attr "type" "veccomplex") (set (attr "length") (if_then_else - (match_test "(BYTES_BIG_ENDIAN || VECTOR_ELT_ORDER_BIG)") + (match_test "(VECTOR_ELT_ORDER_BIG)") (const_string "4") (const_string "12")))]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7a57477..c81a00d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2014-02-05 Bill Schmidt + * gcc.dg/vmx/sum2s.c: New. + * gcc.dg/vmx/sum2s-be-order.c: New. + +2014-02-05 Bill Schmidt + * gcc.dg/vmx/pack.c: New. * gcc.dg/vmx/pack-be-order.c: New. * gcc.dg/vmx/unpack.c: New. diff --git a/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c b/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c new file mode 100644 index 0000000..0981cc1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c @@ -0,0 +1,19 @@ +/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */ + +#include "harness.h" + +static void test() +{ + vector signed int vsia = {-10,1,2,3}; + vector signed int vsib = {100,101,102,-103}; + vector signed int vsir; +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + vector signed int vsier = {91,0,107,0}; +#else + vector signed int vsier = {0,92,0,-98}; +#endif + + vsir = vec_sum2s (vsia, vsib); + + check (vec_all_eq (vsir, vsier), "vsir"); +} diff --git a/gcc/testsuite/gcc.dg/vmx/sum2s.c b/gcc/testsuite/gcc.dg/vmx/sum2s.c new file mode 100644 index 0000000..ded05be --- /dev/null +++ b/gcc/testsuite/gcc.dg/vmx/sum2s.c @@ -0,0 +1,13 @@ +#include "harness.h" + +static void test() +{ + vector signed int vsia = {-10,1,2,3}; + vector signed int vsib = {100,101,102,-103}; + vector signed int vsir; + vector signed int vsier = {0,92,0,-98}; + + vsir = vec_sum2s (vsia, vsib); + + check (vec_all_eq (vsir, vsier), "vsir"); +} -- 2.7.4