From 7b0d89b18486d945372aeab604c145a88353080c Mon Sep 17 00:00:00 2001 From: Egor Bogatov Date: Tue, 29 Dec 2020 00:36:23 +0300 Subject: [PATCH] RyuJIT: Remove redundant memory barrier for XAdd and XChg on arm (#45970) * Remove redundant memory barrier for XAdd and XChg on arm * Update codegenarm64.cpp * Same for casal --- src/coreclr/jit/codegenarm64.cpp | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 752eff9..951fbbc 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2814,20 +2814,12 @@ void CodeGen::genLockedInstructions(GenTreeOp* treeNode) GetEmitter()->emitIns_R_R_R(INS_swpal, dataSize, dataReg, targetReg, addrReg); break; case GT_XADD: - if ((targetReg == REG_NA) || (targetReg == REG_ZR)) - { - GetEmitter()->emitIns_R_R(INS_staddl, dataSize, dataReg, addrReg); - } - else - { - GetEmitter()->emitIns_R_R_R(INS_ldaddal, dataSize, dataReg, targetReg, addrReg); - } + GetEmitter()->emitIns_R_R_R(INS_ldaddal, dataSize, dataReg, (targetReg == REG_NA) ? REG_ZR : targetReg, + addrReg); break; default: assert(!"Unexpected treeNode->gtOper"); } - - instGen_MemoryBarrier(); } else { @@ -2955,8 +2947,6 @@ void CodeGen::genCodeForCmpXchg(GenTreeCmpXchg* treeNode) noway_assert(dataReg != targetReg); } GetEmitter()->emitIns_R_R_R(INS_casal, dataSize, targetReg, dataReg, addrReg); - - instGen_MemoryBarrier(); } else { -- 2.7.4