From 7a94fa58c4fbc495f19e4c812fa85b54e63e6b36 Mon Sep 17 00:00:00 2001
From: Shengchen Kan <shengchen.kan@intel.com>
Date: Sat, 26 Mar 2022 16:33:29 +0800
Subject: [PATCH] [X86][tablgen] Move fields Name, Is64Bit, Is32Bit, Operands
 from RecognizableInstrBase to RecognizableInstr, NFCI

These four fields are not used by any user of `RecognizableInstrBase`,
so we can move them to `RecognizableInstr` to avoid unnecessary
construction.
---
 llvm/utils/TableGen/X86RecognizableInstr.cpp | 35 ++++++++++++----------------
 llvm/utils/TableGen/X86RecognizableInstr.h   | 27 ++++++++++-----------
 2 files changed, 27 insertions(+), 35 deletions(-)

diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 6d857f68..e9fe1e3 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -77,8 +77,6 @@ static uint8_t byteFromRec(const Record* rec, StringRef name) {
 
 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
   Rec = insn.TheDef;
-  Name = std::string(Rec->getName());
-
   if (!Rec->isSubClassOf("X86Inst")) {
     ShouldBeEmitted = false;
     return;
@@ -105,20 +103,30 @@ RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
   ForceDisassemble   = Rec->getValueAsBit("ForceDisassemble");
   CD8_Scale          = byteFromRec(Rec, "CD8_Scale");
 
-  Name = std::string(Rec->getName());
-
-  Operands = &insn.Operands.OperandList;
-
   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
 
   EncodeRC = HasEVEX_B &&
              (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
 
+  if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
+    ShouldBeEmitted = false;
+    return;
+  }
+
+  ShouldBeEmitted = true;
+}
+
+RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
+                                     const CodeGenInstruction &insn,
+                                     InstrUID uid)
+    : RecognizableInstrBase(insn) {
+  Name = std::string(Rec->getName());
+  Operands = &insn.Operands.OperandList;
   // Check for 64-bit inst which does not require REX
   Is32Bit = false;
   Is64Bit = false;
   // FIXME: Is there some better way to check for In64BitMode?
-  std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
+  std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates");
   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
     if (Predicates[i]->getName().contains("Not64Bit") ||
         Predicates[i]->getName().contains("In32Bit")) {
@@ -130,19 +138,6 @@ RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
       break;
     }
   }
-
-  if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
-    ShouldBeEmitted = false;
-    return;
-  }
-
-  ShouldBeEmitted = true;
-}
-
-RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
-                                     const CodeGenInstruction &insn,
-                                     InstrUID uid)
-    : RecognizableInstrBase(insn) {
   UID = uid;
   Spec = &tables.specForUID(UID);
 }
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index bef4024..adf0e326 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -205,23 +205,10 @@ struct RecognizableInstrBase {
   bool ForceDisassemble;
   // The CD8_Scale field from the record
   uint8_t CD8_Scale;
-  // Whether the instruction has the predicate "In64BitMode"
-  bool Is64Bit;
-  // Whether the instruction has the predicate "In32BitMode"
-  bool Is32Bit;
-
-  /// The instruction name as listed in the tables
-  std::string Name;
-
   /// Indicates whether the instruction should be emitted into the decode
   /// tables; regardless, it will be emitted into the instruction info table
   bool ShouldBeEmitted;
 
-  /// The operands of the instruction, as listed in the CodeGenInstruction.
-  /// They are not one-to-one with operands listed in the MCInst; for example,
-  /// memory operands expand to 5 operands in the MCInst
-  const std::vector<CGIOperandList::OperandInfo>* Operands;
-
   /// \param insn The CodeGenInstruction to extract information from.
   RecognizableInstrBase(const CodeGenInstruction &insn);
 };
@@ -231,14 +218,24 @@ struct RecognizableInstrBase {
 ///   to interpret the information available in the LLVM tables, and to emit the
 ///   instruction into DisassemblerTables.
 class RecognizableInstr : public RecognizableInstrBase {
-public:
+private:
+  /// The instruction name as listed in the tables
+  std::string Name;
+  // Whether the instruction has the predicate "In64BitMode"
+  bool Is64Bit;
+  // Whether the instruction has the predicate "In32BitMode"
+  bool Is32Bit;
+  /// The operands of the instruction, as listed in the CodeGenInstruction.
+  /// They are not one-to-one with operands listed in the MCInst; for example,
+  /// memory operands expand to 5 operands in the MCInst
+  const std::vector<CGIOperandList::OperandInfo>* Operands;
+
   /// The opcode of the instruction, as used in an MCInst
   InstrUID UID;
   /// The description of the instruction that is emitted into the instruction
   /// info table
   InstructionSpecifier* Spec;
 
-private:
   /// insnContext - Returns the primary context in which the instruction is
   ///   valid.
   ///
-- 
2.7.4